1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements hazard recognizers for scheduling on PowerPC processors. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "pre-RA-sched" 15 #include "PPCHazardRecognizers.h" 16 #include "PPC.h" 17 #include "PPCInstrInfo.h" 18 #include "llvm/CodeGen/ScheduleDAG.h" 19 #include "llvm/Support/Debug.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/Support/raw_ostream.h" 22 using namespace llvm; 23 24 //===----------------------------------------------------------------------===// 25 // PowerPC 970 Hazard Recognizer 26 // 27 // This models the dispatch group formation of the PPC970 processor. Dispatch 28 // groups are bundles of up to five instructions that can contain various mixes 29 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one 30 // branch instruction per-cycle. 31 // 32 // There are a number of restrictions to dispatch group formation: some 33 // instructions can only be issued in the first slot of a dispatch group, & some 34 // instructions fill an entire dispatch group. Additionally, only branches can 35 // issue in the 5th (last) slot. 36 // 37 // Finally, there are a number of "structural" hazards on the PPC970. These 38 // conditions cause large performance penalties due to misprediction, recovery, 39 // and replay logic that has to happen. These cases include setting a CTR and 40 // branching through it in the same dispatch group, and storing to an address, 41 // then loading from the same address within a dispatch group. To avoid these 42 // conditions, we insert no-op instructions when appropriate. 43 // 44 // FIXME: This is missing some significant cases: 45 // 1. Modeling of microcoded instructions. 46 // 2. Handling of serialized operations. 47 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping". 48 // 49 50 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii) 51 : TII(tii) { 52 EndDispatchGroup(); 53 } 54 55 void PPCHazardRecognizer970::EndDispatchGroup() { 56 DEBUG(errs() << "=== Start of dispatch group\n"); 57 NumIssued = 0; 58 59 // Structural hazard info. 60 HasCTRSet = false; 61 NumStores = 0; 62 } 63 64 65 PPCII::PPC970_Unit 66 PPCHazardRecognizer970::GetInstrType(unsigned Opcode, 67 bool &isFirst, bool &isSingle, 68 bool &isCracked, 69 bool &isLoad, bool &isStore) { 70 if ((int)Opcode >= 0) { 71 isFirst = isSingle = isCracked = isLoad = isStore = false; 72 return PPCII::PPC970_Pseudo; 73 } 74 Opcode = ~Opcode; 75 76 const MCInstrDesc &MCID = TII.get(Opcode); 77 78 isLoad = MCID.mayLoad(); 79 isStore = MCID.mayStore(); 80 81 uint64_t TSFlags = MCID.TSFlags; 82 83 isFirst = TSFlags & PPCII::PPC970_First; 84 isSingle = TSFlags & PPCII::PPC970_Single; 85 isCracked = TSFlags & PPCII::PPC970_Cracked; 86 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask); 87 } 88 89 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer 90 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true. 91 bool PPCHazardRecognizer970:: 92 isLoadOfStoredAddress(unsigned LoadSize, SDValue Ptr1, SDValue Ptr2) const { 93 for (unsigned i = 0, e = NumStores; i != e; ++i) { 94 // Handle exact and commuted addresses. 95 if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i]) 96 return true; 97 if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i]) 98 return true; 99 100 // Okay, we don't have an exact match, if this is an indexed offset, see if 101 // we have overlap (which happens during fp->int conversion for example). 102 if (StorePtr2[i] == Ptr2) { 103 if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i])) 104 if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) { 105 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check 106 // to see if the load and store actually overlap. 107 int StoreOffs = StoreOffset->getZExtValue(); 108 int LoadOffs = LoadOffset->getZExtValue(); 109 if (StoreOffs < LoadOffs) { 110 if (int(StoreOffs+StoreSize[i]) > LoadOffs) return true; 111 } else { 112 if (int(LoadOffs+LoadSize) > StoreOffs) return true; 113 } 114 } 115 } 116 } 117 return false; 118 } 119 120 /// getHazardType - We return hazard for any non-branch instruction that would 121 /// terminate the dispatch group. We turn NoopHazard for any 122 /// instructions that wouldn't terminate the dispatch group that would cause a 123 /// pipeline flush. 124 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970:: 125 getHazardType(SUnit *SU, int Stalls) { 126 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead"); 127 128 const SDNode *Node = SU->getNode()->getGluedMachineNode(); 129 bool isFirst, isSingle, isCracked, isLoad, isStore; 130 PPCII::PPC970_Unit InstrType = 131 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 132 isLoad, isStore); 133 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard; 134 unsigned Opcode = Node->getMachineOpcode(); 135 136 // We can only issue a PPC970_First/PPC970_Single instruction (such as 137 // crand/mtspr/etc) if this is the first cycle of the dispatch group. 138 if (NumIssued != 0 && (isFirst || isSingle)) 139 return Hazard; 140 141 // If this instruction is cracked into two ops by the decoder, we know that 142 // it is not a branch and that it cannot issue if 3 other instructions are 143 // already in the dispatch group. 144 if (isCracked && NumIssued > 2) 145 return Hazard; 146 147 switch (InstrType) { 148 default: llvm_unreachable("Unknown instruction type!"); 149 case PPCII::PPC970_FXU: 150 case PPCII::PPC970_LSU: 151 case PPCII::PPC970_FPU: 152 case PPCII::PPC970_VALU: 153 case PPCII::PPC970_VPERM: 154 // We can only issue a branch as the last instruction in a group. 155 if (NumIssued == 4) return Hazard; 156 break; 157 case PPCII::PPC970_CRU: 158 // We can only issue a CR instruction in the first two slots. 159 if (NumIssued >= 2) return Hazard; 160 break; 161 case PPCII::PPC970_BRU: 162 break; 163 } 164 165 // Do not allow MTCTR and BCTRL to be in the same dispatch group. 166 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4)) 167 return NoopHazard; 168 169 // If this is a load following a store, make sure it's not to the same or 170 // overlapping address. 171 if (isLoad && NumStores) { 172 unsigned LoadSize; 173 switch (Opcode) { 174 default: llvm_unreachable("Unknown load!"); 175 case PPC::LBZ: case PPC::LBZU: 176 case PPC::LBZX: 177 case PPC::LBZ8: case PPC::LBZU8: 178 case PPC::LBZX8: 179 case PPC::LVEBX: 180 LoadSize = 1; 181 break; 182 case PPC::LHA: case PPC::LHAU: 183 case PPC::LHAX: 184 case PPC::LHZ: case PPC::LHZU: 185 case PPC::LHZX: 186 case PPC::LVEHX: 187 case PPC::LHBRX: 188 case PPC::LHA8: case PPC::LHAU8: 189 case PPC::LHAX8: 190 case PPC::LHZ8: case PPC::LHZU8: 191 case PPC::LHZX8: 192 LoadSize = 2; 193 break; 194 case PPC::LFS: case PPC::LFSU: 195 case PPC::LFSX: 196 case PPC::LWZ: case PPC::LWZU: 197 case PPC::LWZX: 198 case PPC::LWA: 199 case PPC::LWAX: 200 case PPC::LVEWX: 201 case PPC::LWBRX: 202 case PPC::LWZ8: 203 case PPC::LWZX8: 204 LoadSize = 4; 205 break; 206 case PPC::LFD: case PPC::LFDU: 207 case PPC::LFDX: 208 case PPC::LD: case PPC::LDU: 209 case PPC::LDX: 210 LoadSize = 8; 211 break; 212 case PPC::LVX: 213 case PPC::LVXL: 214 LoadSize = 16; 215 break; 216 } 217 218 if (isLoadOfStoredAddress(LoadSize, 219 Node->getOperand(0), Node->getOperand(1))) 220 return NoopHazard; 221 } 222 223 return NoHazard; 224 } 225 226 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) { 227 const SDNode *Node = SU->getNode()->getGluedMachineNode(); 228 bool isFirst, isSingle, isCracked, isLoad, isStore; 229 PPCII::PPC970_Unit InstrType = 230 GetInstrType(Node->getOpcode(), isFirst, isSingle, isCracked, 231 isLoad, isStore); 232 if (InstrType == PPCII::PPC970_Pseudo) return; 233 unsigned Opcode = Node->getMachineOpcode(); 234 235 // Update structural hazard information. 236 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true; 237 238 // Track the address stored to. 239 if (isStore) { 240 unsigned ThisStoreSize; 241 switch (Opcode) { 242 default: llvm_unreachable("Unknown store instruction!"); 243 case PPC::STB: case PPC::STB8: 244 case PPC::STBU: case PPC::STBU8: 245 case PPC::STBX: case PPC::STBX8: 246 case PPC::STVEBX: 247 ThisStoreSize = 1; 248 break; 249 case PPC::STH: case PPC::STH8: 250 case PPC::STHU: case PPC::STHU8: 251 case PPC::STHX: case PPC::STHX8: 252 case PPC::STVEHX: 253 case PPC::STHBRX: 254 ThisStoreSize = 2; 255 break; 256 case PPC::STFS: 257 case PPC::STFSU: 258 case PPC::STFSX: 259 case PPC::STWX: case PPC::STWX8: 260 case PPC::STWUX: 261 case PPC::STW: case PPC::STW8: 262 case PPC::STWU: 263 case PPC::STVEWX: 264 case PPC::STFIWX: 265 case PPC::STWBRX: 266 ThisStoreSize = 4; 267 break; 268 case PPC::STD_32: 269 case PPC::STDX_32: 270 case PPC::STD: 271 case PPC::STDU: 272 case PPC::STFD: 273 case PPC::STFDX: 274 case PPC::STDX: 275 case PPC::STDUX: 276 ThisStoreSize = 8; 277 break; 278 case PPC::STVX: 279 case PPC::STVXL: 280 ThisStoreSize = 16; 281 break; 282 } 283 284 StoreSize[NumStores] = ThisStoreSize; 285 StorePtr1[NumStores] = Node->getOperand(1); 286 StorePtr2[NumStores] = Node->getOperand(2); 287 ++NumStores; 288 } 289 290 if (InstrType == PPCII::PPC970_BRU || isSingle) 291 NumIssued = 4; // Terminate a d-group. 292 ++NumIssued; 293 294 // If this instruction is cracked into two ops by the decoder, remember that 295 // we issued two pieces. 296 if (isCracked) 297 ++NumIssued; 298 299 if (NumIssued == 5) 300 EndDispatchGroup(); 301 } 302 303 void PPCHazardRecognizer970::AdvanceCycle() { 304 assert(NumIssued < 5 && "Illegal dispatch group!"); 305 ++NumIssued; 306 if (NumIssued == 5) 307 EndDispatchGroup(); 308 } 309
