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      1 /*
      2  * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 
      7 #ifndef __MCE_H__
      8 #define __MCE_H__
      9 
     10 #include <mmio.h>
     11 #include <tegra_def.h>
     12 
     13 /*******************************************************************************
     14  * MCE commands
     15  ******************************************************************************/
     16 typedef enum mce_cmd {
     17 	MCE_CMD_ENTER_CSTATE = 0U,
     18 	MCE_CMD_UPDATE_CSTATE_INFO = 1U,
     19 	MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
     20 	MCE_CMD_READ_CSTATE_STATS = 3U,
     21 	MCE_CMD_WRITE_CSTATE_STATS = 4U,
     22 	MCE_CMD_IS_SC7_ALLOWED = 5U,
     23 	MCE_CMD_ONLINE_CORE = 6U,
     24 	MCE_CMD_CC3_CTRL = 7U,
     25 	MCE_CMD_ECHO_DATA = 8U,
     26 	MCE_CMD_READ_VERSIONS = 9U,
     27 	MCE_CMD_ENUM_FEATURES = 10U,
     28 	MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
     29 	MCE_CMD_ENUM_READ_MCA = 12U,
     30 	MCE_CMD_ENUM_WRITE_MCA = 13U,
     31 	MCE_CMD_ROC_FLUSH_CACHE = 14U,
     32 	MCE_CMD_ROC_CLEAN_CACHE = 15U,
     33 	MCE_CMD_ENABLE_LATIC = 16U,
     34 	MCE_CMD_UNCORE_PERFMON_REQ = 17U,
     35 	MCE_CMD_MISC_CCPLEX = 18U,
     36 	MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
     37 	MCE_CMD_MAX = 0xFFU,
     38 } mce_cmd_t;
     39 
     40 #define MCE_CMD_MASK				0xFFU
     41 
     42 /*******************************************************************************
     43  * Timeout value used to powerdown a core
     44  ******************************************************************************/
     45 #define MCE_CORE_SLEEP_TIME_INFINITE		0xFFFFFFFFU
     46 
     47 /*******************************************************************************
     48  * Struct to prepare UPDATE_CSTATE_INFO request
     49  ******************************************************************************/
     50 typedef struct mce_cstate_info {
     51 	/* cluster cstate value */
     52 	uint32_t cluster;
     53 	/* ccplex cstate value */
     54 	uint32_t ccplex;
     55 	/* system cstate value */
     56 	uint32_t system;
     57 	/* force system state? */
     58 	uint8_t system_state_force;
     59 	/* wake mask value */
     60 	uint32_t wake_mask;
     61 	/* update the wake mask? */
     62 	uint8_t update_wake_mask;
     63 } mce_cstate_info_t;
     64 
     65 /* public interfaces */
     66 int mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
     67 		uint64_t arg2);
     68 int mce_update_reset_vector(void);
     69 int mce_update_gsc_videomem(void);
     70 int mce_update_gsc_tzdram(void);
     71 int mce_update_gsc_tzram(void);
     72 __dead2 void mce_enter_ccplex_state(uint32_t state_idx);
     73 void mce_update_cstate_info(const mce_cstate_info_t *cstate);
     74 void mce_verify_firmware_version(void);
     75 
     76 #endif /* __MCE_H__ */
     77