| /art/tools/dexfuzz/src/dexfuzz/program/mutators/ |
| ArithOpChanger.java | 25 import dexfuzz.rawdex.Opcode;
144 stats.incrementStat("Changed arithmetic opcode");
151 Opcode opcode = mInsn.insn.info.opcode; local
152 if (Opcode.isBetween(opcode, Opcode.ADD_INT, Opcode.USHR_INT_LIT8)) {
158 private Opcode getLegalDifferentOpcode(MInsn mInsn)
159 Opcode opcode = mInsn.insn.info.opcode; local
[all...] |
| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/builder/ |
| PayloadAlignmentTest.java | 35 import org.jf.dexlib2.Opcode;
53 implBuilder.addInstruction(new BuilderInstruction10x(Opcode.NOP));
63 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
70 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
79 Assert.assertEquals(instruction.getOpcode(), Opcode.MOVE);
82 Assert.assertEquals(instruction.getOpcode(), Opcode.NOP);
85 Assert.assertEquals(instruction.getOpcode(), Opcode.ARRAY_PAYLOAD);
93 implBuilder.addInstruction(new BuilderInstruction31t(Opcode.FILL_ARRAY_DATA, 0, label));
94 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0));
95 implBuilder.addInstruction(new BuilderInstruction12x(Opcode.MOVE, 0, 0))
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
|
| ThumbRegisterInfo.cpp | 336 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
338 static unsigned convertToNonSPOpcode(unsigned Opcode) {
339 switch (Opcode) {
347 return Opcode;
360 unsigned Opcode = MI.getOpcode();
364 if (Opcode == ARM::tADDframe) {
396 unsigned NewOpc = convertToNonSPOpcode(Opcode);
397 if (NewOpc != Opcode && FrameReg != ARM::SP)
408 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMHazardRecognizer.cpp | 26 unsigned Opcode = MCID.getOpcode();
27 if (Opcode == ARM::VMOVRS || Opcode == ARM::VMOVRRD)
85 unsigned Opcode = MI->getOpcode();
88 } else if (Opcode == ARM::t2IT) {
|
| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 82 enum prog_opcode Opcode;
90 * \note Opcode should equal array index!
157 * Return the number of src registers for the given instruction/opcode.
160 _mesa_num_inst_src_regs(enum prog_opcode opcode)
162 assert(opcode < MAX_OPCODE);
163 assert(opcode == InstInfo[opcode].Opcode);
164 assert(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
165 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8632/ |
| X87.cpp | 70 constexpr uint8_t Opcode = 0xd9;
73 verifyBytes<ByteCount>(codeBytes(), Opcode, ModRM, 0x45, 0x23, 0x01, 0x00);
83 constexpr uint8_t Opcode = 0xd9;
86 verifyBytes<ByteCount>(codeBytes(), Opcode, ModRM, 0x45, 0x23, 0x01, 0x00);
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/Network/Mtftp4Dxe/ |
| Mtftp4Wrq.c | 57 Packet->Data.OpCode = HTONS (EFI_MTFTP4_OPCODE_DATA);
315 Bogus.Ack.OpCode = HTONS (EFI_MTFTP4_OPCODE_ACK);
352 UINT16 Opcode;
404 Opcode = NTOHS (Packet->OpCode);
411 ((Opcode == EFI_MTFTP4_OPCODE_OACK) || (Opcode == EFI_MTFTP4_OPCODE_ERROR))) {
424 if (Opcode != EFI_MTFTP4_OPCODE_ERROR) {
437 switch (Opcode) {
|
| /device/linaro/bootloader/edk2/NetworkPkg/Mtftp6Dxe/ |
| Mtftp6Wrq.c | 61 Packet->Data.OpCode = HTONS (EFI_MTFTP6_OPCODE_DATA);
360 Dummy.Ack.OpCode = HTONS (EFI_MTFTP6_OPCODE_ACK);
397 UINT16 Opcode;
455 Opcode = NTOHS (Packet->OpCode);
462 (Opcode == EFI_MTFTP6_OPCODE_OACK || Opcode == EFI_MTFTP6_OPCODE_ERROR)
476 if (Opcode != EFI_MTFTP6_OPCODE_ERROR) {
501 switch (Opcode) {
|
| /external/capstone/ |
| MCInst.h | 96 unsigned Opcode;
|
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 24 enum Opcode {
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
|
| /external/llvm/lib/Target/ARM/InstPrinter/ |
| ARMInstPrinter.cpp | 73 unsigned Opcode = MI->getOpcode();
75 switch (Opcode) {
134 if (Opcode == ARM::t2STMDB_UPD)
163 if (Opcode == ARM::t2LDMIA_UPD)
243 bool isStore = Opcode == ARM::STREXD || Opcode == ARM::STLEXD;
248 NewMI.setOpcode(Opcode);
785 unsigned Opcode = MI->getOpcode();
788 if (Opcode == ARM::t2MSR_M && FeatureBits[ARM::FeatureDSP]) {
820 if (Opcode == ARM::t2MSR_M && FeatureBits [ARM::HasV7Ops])
[all...] |
| /external/llvm/lib/Target/AVR/ |
| AVRRegisterInfo.cpp | 94 int Opcode = MI.getOpcode();
97 if ((Opcode != AVR::SUBIWRdK) && (Opcode != AVR::ADIWRdK)) {
108 switch (Opcode) {
152 unsigned Opcode;
166 // Select the best opcode based on DstReg and the offset size.
172 Opcode = AVR::ADIWRdK;
178 // This opcode will get expanded into a pair of subi/sbci.
179 Opcode = AVR::SUBIWRdK;
185 MachineInstr *New = BuildMI(MBB, std::next(II), dl, TII.get(Opcode), DstReg
[all...] |
| /external/llvm/lib/Target/BPF/ |
| BPFISelDAGToDAG.cpp | 119 unsigned Opcode = Node->getOpcode();
131 switch (Opcode) {
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 111 unsigned Opcode = MI.getOpcode();
115 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiISelDAGToDAG.cpp | 274 unsigned Opcode = Node->getOpcode();
287 switch (Opcode) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 93 unsigned Opcode = MI->getOpcode();
94 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
110 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
|
| /external/mesa3d/src/mesa/main/ |
| atifragshader.h | 23 GLenum opcode; member in struct:ati_fs_opcode_st
50 GLenum Opcode[2];
59 GLenum Opcode;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
| MBlazeMCCodeEmitter.cpp | 182 unsigned Opcode = MI.getOpcode();
183 const MCInstrDesc &Desc = MCII.get(Opcode);
|
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCHazardRecognizers.cpp | 66 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
70 if ((int)Opcode >= 0) {
74 Opcode = ~Opcode;
76 const MCInstrDesc &MCID = TII.get(Opcode);
134 unsigned Opcode = Node->getMachineOpcode();
166 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
173 switch (Opcode) {
233 unsigned Opcode = Node->getMachineOpcode()
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 165 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
166 return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
174 unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
175 SDNode *Mul = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Glue,
|
| SparcInstrInfo.cpp | 166 unsigned Opcode = I->getOpcode();
167 if (Opcode != SP::BCOND && Opcode != SP::FBCOND)
168 return true; //Unknown Opcode
194 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(Opcode))
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 24 enum Opcode {
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
|
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/CodeGen/GlobalISel/ |
| LegalizerInfo.h | 33 /// Legalization is decided based on an instruction's opcode, which type slot
37 unsigned Opcode;
41 InstrAspect(unsigned Opcode, LLT Type) : Opcode(Opcode), Idx(0), Type(Type) {}
42 InstrAspect(unsigned Opcode, unsigned Idx, LLT Type)
43 : Opcode(Opcode), Idx(Idx), Type(Type) {}
46 return Opcode == RHS.Opcode && Idx == RHS.Idx && Type == RHS.Type
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/clang/Analysis/Analyses/ |
| ThreadSafetyLogical.h | 24 enum Opcode {
30 Opcode kind() const { return Kind; }
37 LExpr(Opcode Kind) : Kind(Kind) {}
40 Opcode Kind;
59 BinOp(LExpr *LHS, LExpr *RHS, Opcode Code) : LExpr(Code), LHS(LHS), RHS(RHS) {}
|
