1 /** @file 2 * 3 * Copyright (c) 2016, Hisilicon Limited. All rights reserved. 4 * Copyright (c) 2016, Linaro Limited. All rights reserved. 5 * 6 * This program and the accompanying materials 7 * are licensed and made available under the terms and conditions of the BSD License 8 * which accompanies this distribution. The full text of the license may be found at 9 * http://opensource.org/licenses/bsd-license.php 10 * 11 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 * 14 **/ 15 16 #ifndef __PCIE_KERNEL_API_H__ 17 #define __PCIE_KERNEL_API_H__ 18 19 #define PCIE_HOST_BRIDGE_NUM (1) 20 #define PCIE_MAX_PORT_NUM (4) 21 #define PCIE_MAX_OUTBOUND (6) 22 #define PCIE_MAX_INBOUND (4) 23 #define PCIE3_MAX_OUTBOUND (16) 24 #define PCIE3_MAX_INBOUND (16) 25 26 #define PCIE_LINK_LOOP_CNT (0x1000) 27 #define PCIE_IATU_ADDR_MASK (0xFFFFF000) 28 #define PCIE_1M_ALIGN_SHIRFT (20) 29 #define PCIE_BDF_MASK (0xF0000FFF) 30 #define PCIE_BUS_SHIRFT (20) 31 #define PCIE_DEV_SHIRFT (15) 32 #define PCIE_FUNC_SHIRFT (12) 33 34 #define PCIE_DBI_CS2_ENABLE (0x1) 35 #define PCIE_DBI_CS2_DISABLE (0x0) 36 37 #define PCIE_DMA_CHANLE_READ (0x1) 38 #define PCIE_DMA_CHANLE_WRITE (0x0) 39 40 41 #define PCIE_ERR_IATU_TABLE_NULL EFIERR (1) 42 #define PCIE_ERR_LINK_OVER_TIME EFIERR (2) 43 #define PCIE_ERR_UNIMPLEMENT_PCIE_TYPE EFIERR (3) 44 #define PCIE_ERR_ALREADY_INIT EFIERR (4) 45 #define PCIE_ERR_PARAM_INVALID EFIERR (5) 46 #define PCIE_ERR_MEM_OPT_OVER EFIERR (6) 47 #define PCIE_ERR_NOT_INIT EFIERR (7) 48 #define PCIE_ERR_CFG_OPT_OVER EFIERR (8) 49 #define PCIE_ERR_DMA_READ_CHANLE_BUSY EFIERR (9) 50 #define PCIE_ERR_DMA_WRITE_CHANLE_BUSY EFIERR (10) 51 #define PCIE_ERR_DMAR_NO_RESORCE EFIERR (11) 52 #define PCIE_ERR_DMAW_NO_RESORCE EFIERR (12) 53 #define PCIE_ERR_DMA_OVER_MAX_RESORCE EFIERR (13) 54 #define PCIE_ERR_NO_IATU_WINDOW EFIERR (14) 55 #define PCIE_ERR_DMA_TRANSPORT_OVER_TIME EFIERR (15) 56 #define PCIE_ERR_DMA_MEM_ALLOC_ERROR EFIERR (16) 57 #define PCIE_ERR_DMA_ABORT EFIERR (17) 58 #define PCIE_ERR_UNSUPPORT_BAR_TYPE EFIERR (18) 59 60 typedef enum { 61 PCIE_ROOT_COMPLEX, 62 PCIE_END_POINT, 63 PCIE_NTB_TO_NTB, 64 PCIE_NTB_TO_RP, 65 } PCIE_PORT_TYPE; 66 67 typedef enum { 68 PCIE_GEN1_0 = 1, //PCIE 1.0 69 PCIE_GEN2_0 = 2, //PCIE 2.0 70 PCIE_GEN3_0 = 4 //PCIE 3.0 71 } PCIE_PORT_GEN; 72 73 typedef enum { 74 PCIE_WITDH_X1 = 0x1, 75 PCIE_WITDH_X2 = 0x3, 76 PCIE_WITDH_X4 = 0x7, 77 PCIE_WITDH_X8 = 0xf, 78 PCIE_WITDH_INVALID 79 } PCIE_PORT_WIDTH; 80 81 82 typedef struct { 83 PCIE_PORT_TYPE PortType; 84 PCIE_PORT_WIDTH PortWidth; 85 PCIE_PORT_GEN PortGen; 86 UINT8 PcieLinkUp; 87 } PCIE_PORT_INFO; 88 89 typedef struct tagPciecfg_params 90 { 91 UINT32 preemphasis; 92 UINT32 deemphasis; 93 UINT32 swing; 94 UINT32 balance; 95 }pcie_cfg_params_s; 96 97 typedef enum { 98 PCIE_CORRECTABLE_ERROR = 0, 99 PCIE_NON_FATAL_ERROR, 100 PCIE_FATAL_ERROR, 101 PCIE_UNSUPPORTED_REQUEST_ERROR, 102 PCIE_ALL_ERROR 103 } PCIE_ERROR_TYPE; 104 105 typedef union tagPcieDeviceStatus 106 { 107 struct 108 { 109 UINT16 correctable_error : 1; 110 UINT16 non_fatal_error : 1; 111 UINT16 fatal_error : 1; 112 UINT16 unsupported_error : 1; 113 UINT16 aux_power : 1; 114 UINT16 transaction_pending : 1; 115 UINT16 reserved_6_15 : 10; 116 }Bits; 117 118 UINT16 Value; 119 }pcie_device_status_u; 120 121 122 typedef union tagPcieUcAerStatus 123 { 124 struct 125 { 126 UINT32 undefined : 1 ; /* [0] undefined */ 127 UINT32 reserved_1_3 : 3 ; /* reserved */ 128 UINT32 data_link_proto_error : 1 ; /* Data Link Protocol Error Status */ 129 UINT32 reserved_5_11 : 7 ; /* reserved */ 130 UINT32 poisoned_tlp_status : 1 ; /* Poisoned TLP Status */ 131 UINT32 flow_control_proto_error : 1 ; /* Flow Control Protocol Error Status */ 132 UINT32 completion_time_out : 1 ; /* Completion Timeout Status */ 133 UINT32 compler_abort_status : 1 ; /* Completer Abort Status */ 134 UINT32 unexpect_completion_status : 1 ; /* Unexpected Completion Status */ 135 UINT32 receiver_overflow_status : 1 ; /*Receiver Overflow Status */ 136 UINT32 malformed_tlp_status : 1 ; /* Malformed TLP Status*/ 137 UINT32 ecrc_error_status : 1 ; /* ECRC Error Status */ 138 UINT32 unsupport_request_error_status : 1 ; /* Unsupported Request Error Status */ 139 UINT32 reserved_21 : 1 ; /* reserved */ 140 UINT32 uncorrectable_interal_error : 1 ; /* Uncorrectable Internal Error Status */ 141 UINT32 reserved_23 : 1 ; /* reserved*/ 142 UINT32 atomicop_egress_blocked_status : 1 ; /* AtomicOp Egress Blocked Status */ 143 UINT32 tlp_prefix_blocked_error_status : 1 ; /* TLP Prefix Blocked Error Status */ 144 UINT32 reserved_26_31 : 1 ; /* reserved */ 145 }Bits; 146 147 UINT32 Value; 148 }pcie_uc_aer_status_u; 149 150 typedef union tagPcieCoAerStatus 151 { 152 struct 153 { 154 UINT32 receiver_error_status : 1 ; /* Receiver Error Status */ 155 UINT32 reserved_1_5 : 5 ; /* Reserved */ 156 UINT32 bad_tlp_status : 1 ; /* Bad TLP Status */ 157 UINT32 bad_dllp_status : 1 ; /* Bad DLLP Status */ 158 UINT32 reply_num_rollover_status : 1 ; /* REPLAY_NUM Rollover Status*/ 159 UINT32 reserved_9_11 : 3 ; /* Reserved */ 160 UINT32 reply_timer_timeout : 1 ; /* Replay Timer Timeout Status */ 161 UINT32 advisory_nonfatal_error : 1 ; /* Advisory Non-Fatal Error Status*/ 162 UINT32 corrected_internal_error : 1 ; /*Corrected Internal Error Status*/ 163 UINT32 reserved_15_31 : 1 ; /* Reserved */ 164 }Bits; 165 UINT32 Value; 166 }pcie_co_aer_status_u; 167 168 typedef struct tagPcieAerStatus 169 { 170 pcie_uc_aer_status_u uc_aer_status; 171 pcie_co_aer_status_u co_aer_status; 172 }pcie_aer_status_s; 173 174 175 176 typedef struct tagPcieLoopTestResult 177 { 178 UINT32 tx_pkts_cnt; 179 UINT32 rx_pkts_cnt; 180 UINT32 error_pkts_cnt; 181 UINT32 droped_pkts_cnt; 182 UINT32 push_cnt; 183 pcie_device_status_u device_status; 184 pcie_aer_status_s pcie_aer_status; 185 } pcie_loop_test_result_s; 186 187 typedef struct tagPcieDmaChannelAttrs { 188 UINT32 dma_chan_en; 189 UINT32 dma_mode; 190 UINT32 channel_status; 191 }pcie_dma_channel_attrs_s; 192 193 typedef enum tagPcieDmaChannelStatus 194 { 195 PCIE_DMA_CS_RESERVED = 0, 196 PCIE_DMA_CS_RUNNING = 1, 197 PCIE_DMA_CS_HALTED = 2, 198 PCIE_DMA_CS_STOPPED = 3 199 }pcie_dma_channel_status_e; 200 201 typedef enum tagPcieDmaIntType{ 202 PCIE_DMA_INT_TYPE_DONE=0, 203 PCIE_DMA_INT_TYPE_ABORT, 204 PCIE_DMA_INT_ALL, 205 PCIE_DMA_INT_NONE 206 }pcie_dma_int_type_e; 207 208 typedef enum tagPcieMulWinSize 209 { 210 WIN_SIZE_4K = 0xc, 211 WIN_SIZE_8K, 212 WIN_SIZE_16K, 213 WIN_SIZE_32K, 214 WIN_SIZE_64K, 215 WIN_SIZE_128K, 216 WIN_SIZE_256K, 217 WIN_SIZE_512K, 218 WIN_SIZE_1M, 219 WIN_SIZE_2M, 220 WIN_SIZE_4M, 221 WIN_SIZE_8M, 222 WIN_SIZE_16M, 223 WIN_SIZE_32M, 224 WIN_SIZE_64M, 225 WIN_SIZE_128M, 226 WIN_SIZE_256M, 227 WIN_SIZE_512M, 228 WIN_SIZE_1G, 229 WIN_SIZE_2G, 230 WIN_SIZE_4G, 231 WIN_SIZE_8G, 232 WIN_SIZE_16G, 233 WIN_SIZE_32G, 234 WIN_SIZE_64G, 235 WIN_SIZE_128G, 236 WIN_SIZE_256G, 237 WIN_SIZE_512G = 0x27, 238 }pcie_mul_win_size_e; 239 240 typedef struct tagPcieMultiCastCfg 241 { 242 UINT64 multicast_base_addr; 243 pcie_mul_win_size_e base_addr_size; 244 UINT64 base_translate_addr; 245 }pcie_multicast_cfg_s; 246 247 typedef enum tagPcieMode 248 { 249 PCIE_EP_DEVICE = 0x0, 250 LEGACY_PCIE_EP_DEVICE = 0x1, 251 RP_OF_PCIE_RC = 0x4, 252 PCIE_INVALID = 0x100 253 }pcie_mode_e; 254 255 typedef struct{ 256 UINT32 PortIndex; 257 PCIE_PORT_INFO PortInfo; 258 UINT64 iep_bar01; /*iep bar 01*/ 259 UINT64 iep_bar23; 260 UINT64 iep_bar45; 261 UINT64 iep_bar01_xlat; 262 UINT64 iep_bar23_xlat; 263 UINT64 iep_bar45_xlat; 264 UINT64 iep_bar_lmt23; 265 UINT64 iep_bar_lmt45; /*bar limit*/ 266 UINT64 eep_bar01; 267 UINT64 eep_bar23; 268 UINT64 eep_bar45; 269 UINT64 eep_bar23_xlat; 270 UINT64 eep_bar45_xlat; 271 UINT64 eep_bar_lmt23; /*bar limit*/ 272 UINT64 eep_bar_lmt45; /*bar limit*/ 273 } PCIE_NTB_CFG; 274 275 extern int pcie_mode_get(UINT32 Port, PCIE_PORT_INFO *port_info); 276 277 extern int pcie_port_ctrl(UINT32 Port, UINT32 port_ctrl); 278 279 extern int pcie_link_speed_set(UINT32 Port, PCIE_PORT_GEN speed); 280 281 extern int pcie_port_cfg_set(UINT32 Port, pcie_cfg_params_s *cfg_params); 282 283 extern int pcie_port_cfg_get(UINT32 Port, pcie_cfg_params_s *cfg_params); 284 285 286 extern int pcie_dma_chan_ctl(UINT32 Port,UINT32 channel,UINT32 control); 287 288 extern int pcie_dma_chan_attribu_set(UINT32 Port,UINT32 channel, pcie_dma_channel_attrs_s *dma_attribute); 289 290 extern int pcie_dma_cur_status_get(UINT32 Port, UINT32 channel, pcie_dma_channel_status_e *dma_channel_status); 291 292 extern int pcie_dma_int_enable(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type); 293 294 extern int pcie_dma_int_mask(UINT32 Port, UINT32 channel, pcie_dma_int_type_e int_type); 295 296 extern int pcie_dma_tranfer_stop(UINT32 Port, UINT32 channel); 297 298 299 extern int pcie_dma_int_status_get(UINT32 Port, UINT32 channel, int *dma_int_status); 300 301 extern int pcie_dma_int_clear(UINT32 Port, UINT32 channel, pcie_dma_int_type_e dma_int_type); 302 303 304 extern int pcie_dma_read(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size); 305 306 extern int pcie_dma_write(UINT32 Port,void *source, void *dest,UINT32 transfer_size, UINT32 burst_size); 307 308 extern int pcie_multicast_cfg_set(UINT32 Port,pcie_multicast_cfg_s *multicast_cfg,UINT32 win_num); 309 310 extern int pcie_setup_ntb(UINT32 Port, PCIE_NTB_CFG *ntb_cfg); 311 312 extern int pcie_ntb_doorbell_send(UINT32 Port,UINT32 doorbell); 313 314 extern int pcie_loop_test_start(UINT32 Port, UINT32 loop_type); 315 316 extern int pcie_loop_test_stop(UINT32 Port, UINT32 loop_type); 317 318 extern int pcie_loop_test_get(UINT32 Port, UINT32 loop_type, pcie_loop_test_result_s *test_result); 319 extern int pcie_port_reset(UINT32 Port); 320 321 extern int pcie_port_error_report_enable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error); 322 323 extern int pcie_port_error_report_disable(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, PCIE_ERROR_TYPE pcie_error); 324 325 extern int pcie_device_error_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 clear, \ 326 pcie_device_status_u *pcie_stat); 327 extern int pcie_port_aer_cap_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,UINT32 *aer_cap); 328 329 extern int pcie_port_aer_status_get(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func,pcie_uc_aer_status_u *pcie_aer_status); 330 extern int pcie_port_aer_status_clr(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func); 331 332 extern int pcie_port_aer_report_enable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type); 333 334 335 extern int pcie_port_aer_report_disable(UINT32 Port, PCIE_ERROR_TYPE pcie_aer_type); 336 337 338 extern int pcie_cfg_read(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT32 * value, UINT32 length); 339 340 extern int pcie_cfg_write(UINT32 Port, UINT32 bus, UINT32 dev, UINT32 func, UINT32 reg_offset, UINT8 * data, UINT32 length); 341 342 extern int pcie_mem_read(UINT32 Port,void * local_addr, void *pcie_mem_addr,UINT32 length); 343 344 extern int pcie_mem_write(UINT32 Port,void *local_addr , void *pcie_mem_addr,UINT32 length); 345 346 #endif 347
