1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __HIKEY960_DEF_H__ 8 #define __HIKEY960_DEF_H__ 9 10 #include <common_def.h> 11 #include <tbbr_img_def.h> 12 13 #define DDR_BASE 0x0 14 #define DDR_SIZE 0xC0000000 15 16 #define DEVICE_BASE 0xE0000000 17 #define DEVICE_SIZE 0x20000000 18 19 /* Memory location options for TSP */ 20 #define HIKEY960_SRAM_ID 0 21 #define HIKEY960_DRAM_ID 1 22 23 /* 24 * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several 25 * regions: 26 * - Secure DDR (default is the top 16MB) used by OP-TEE 27 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB) 28 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature 29 * - Non-secure DDR (8MB) reserved for OP-TEE's future use 30 */ 31 #define DDR_SEC_SIZE 0x01000000 32 #define DDR_SEC_BASE 0x3F000000 33 34 #define DDR_SDP_SIZE 0x00400000 35 #define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \ 36 DDR_SDP_SIZE) 37 38 /* 39 * PL011 related constants 40 */ 41 #define PL011_UART5_BASE 0xFDF05000 42 #define PL011_UART6_BASE 0xFFF32000 43 #define PL011_BAUDRATE 115200 44 #define PL011_UART_CLK_IN_HZ 19200000 45 46 #define UFS_BASE 0 47 /* FIP partition */ 48 #define HIKEY960_FIP_BASE (UFS_BASE + 0x1400000) 49 #define HIKEY960_FIP_MAX_SIZE (12 << 20) 50 51 #define HIKEY960_UFS_DESC_BASE 0x20000000 52 #define HIKEY960_UFS_DESC_SIZE 0x00200000 /* 2MB */ 53 #define HIKEY960_UFS_DATA_BASE 0x10000000 54 #define HIKEY960_UFS_DATA_SIZE 0x0A000000 /* 160MB */ 55 56 #endif /* __HIKEY960_DEF_H__ */ 57
