1 /* 2 * Copyright (c) 2011 Intel Corporation. All Rights Reserved. 3 * Copyright (c) Imagination Technologies Limited, UK 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 20 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 * 25 * Authors: 26 * Waldo Bastian <waldo.bastian (at) intel.com> 27 * Zeng Li <zeng.li (at) intel.com> 28 * 29 */ 30 31 #ifndef _PNW_CMDBUF_H_ 32 #define _PNW_CMDBUF_H_ 33 34 #include "psb_drv_video.h" 35 #include "psb_surface.h" 36 #include "psb_buffer.h" 37 #ifdef ANDROID 38 #include <drm/ttm/ttm_placement.h> 39 #include <linux/psb_drm.h> 40 #else 41 #include <psb_drm.h> 42 #endif 43 44 #include <stdint.h> 45 46 #define MTX_CMDWORD_ID_MASK (0x7f) 47 #define MTX_CMDWORD_ID_SHIFT (0) 48 #define MTX_CMDWORD_CORE_MASK (0xff) 49 #define MTX_CMDWORD_CORE_SHIFT (8) 50 #define MTX_CMDWORD_COUNT_MASK (0x7fff) 51 #define MTX_CMDWORD_COUNT_SHIFT (16) 52 #define MTX_CMDWORD_INT_SHIFT (7) 53 #define MTX_CMDWORD_INT_MASK (1) 54 55 #define PNW_CMDBUF_START_PIC_IDX (0) 56 #define PNW_CMDBUF_SEQ_HEADER_IDX (1) 57 #define PNW_CMDBUF_PIC_HEADER_IDX (2) 58 #define PNW_CMDBUF_SEI_BUF_PERIOD_IDX (3) 59 #define PNW_CMDBUF_SEI_PIC_TIMING_IDX (4) 60 #define PNW_CMDBUF_SAVING_MAX (5) 61 62 struct pnw_cmdbuf_s { 63 struct psb_buffer_s buf; 64 unsigned int size; 65 66 /* Relocation records */ 67 unsigned char *reloc_base; 68 struct drm_psb_reloc *reloc_idx; 69 70 /* CMD stream data */ 71 int cmd_count; 72 unsigned char *cmd_base; 73 unsigned char *cmd_start; 74 uint32_t *cmd_idx; 75 uint32_t *cmd_idx_saved[PNW_CMDBUF_SAVING_MAX]; /* idx saved for dual-core adjustion */ 76 77 /* all frames share one topaz param buffer which contains InParamBase 78 * AboveParam/BellowParam, and the buffer allocated when the context is created 79 */ 80 struct psb_buffer_s *topaz_in_params_I; 81 unsigned char *topaz_in_params_I_p; 82 83 struct psb_buffer_s *topaz_in_params_P; 84 unsigned char *topaz_in_params_P_p; 85 86 struct psb_buffer_s *topaz_below_params; 87 unsigned char *topaz_below_params_p; 88 89 /* Every frame has its own PIC_PARAMS, SLICE_PARAMS and HEADER mem 90 */ 91 92 /* PicParams: */ 93 struct psb_buffer_s pic_params; 94 unsigned char *pic_params_p; 95 96 /* SeqHeaderMem PicHeaderMem EOSeqHeaderMem EOStreamHeaderMem SliceHeaderMem[MAX_SLICES_PER_PICTURE]*/ 97 struct psb_buffer_s header_mem; 98 unsigned char *header_mem_p; 99 100 /*SliceParams[MAX_SLICES_PER_PICTURE] */ 101 struct psb_buffer_s slice_params; 102 unsigned char *slice_params_p; 103 104 /* AboveParams[MAX_TOPAZ_CORES]; */ 105 struct psb_buffer_s *topaz_above_params; 106 unsigned char *topaz_above_params_p; 107 108 /* Referenced buffers */ 109 psb_buffer_p *buffer_refs; 110 int buffer_refs_count; 111 int buffer_refs_allocated; 112 113 }; 114 115 typedef struct pnw_cmdbuf_s *pnw_cmdbuf_p; 116 117 /* 118 * Create command buffer 119 */ 120 VAStatus pnw_cmdbuf_create(object_context_p obj_context, 121 psb_driver_data_p driver_data, 122 pnw_cmdbuf_p cmdbuf 123 ); 124 125 /* 126 * Destroy buffer 127 */ 128 void pnw_cmdbuf_destroy(pnw_cmdbuf_p cmdbuf); 129 130 /* 131 * Reset buffer & map 132 * 133 * Returns 0 on success 134 */ 135 int pnw_cmdbuf_reset(pnw_cmdbuf_p cmdbuf); 136 137 /* 138 * Unmap buffer 139 * 140 * Returns 0 on success 141 */ 142 int pnw_cmdbuf_unmap(pnw_cmdbuf_p cmdbuf); 143 144 /* 145 * Reference an addtional buffer "buf" in the command stream 146 * Returns a reference index that can be used to refer to "buf" in 147 * relocation records, on error -1 is returned. 148 */ 149 int pnw_cmdbuf_buffer_ref(pnw_cmdbuf_p cmdbuf, psb_buffer_p buf); 150 151 /* Creates a relocation record for a DWORD in the mapped "cmdbuf" at address 152 * "addr_in_cmdbuf" 153 * The relocation is based on the device virtual address of "ref_buffer" 154 * "buf_offset" is be added to the device virtual address, and the sum is then 155 * right shifted with "align_shift". 156 * "mask" determines which bits of the target DWORD will be updated with the so 157 * constructed address. The remaining bits will be filled with bits from "background". 158 */ 159 void pnw_cmdbuf_add_relocation(pnw_cmdbuf_p cmdbuf, 160 uint32_t *addr_in_dst_buffer,/*addr of dst_buffer for the DWORD*/ 161 psb_buffer_p ref_buffer, 162 uint32_t buf_offset, 163 uint32_t mask, 164 uint32_t background, 165 uint32_t align_shift, 166 uint32_t dst_buffer, /*Index of the list refered by cmdbuf->buffer_refs */ 167 uint32_t *start_of_dst_buffer); 168 169 #define RELOC_CMDBUF_PNW(dest, offset, buf) pnw_cmdbuf_add_relocation(cmdbuf, (uint32_t*)(dest), buf, offset, 0XFFFFFFFF, 0, 0, 0, (uint32_t *)cmdbuf->cmd_start) 170 171 /* do relocation in PIC_PARAMS: src/dst Y/UV base, InParamsBase, CodeBase, BellowParamsBase, AboveParamsBase */ 172 #define RELOC_PIC_PARAMS_PNW(dest, offset, buf) pnw_cmdbuf_add_relocation(cmdbuf, (uint32_t*)(dest), buf, offset, 0XFFFFFFFF, 0, 0, 1, (uint32_t *)cmdbuf->pic_params_p) 173 174 /* do relocation in SLICE_PARAMS: reference Y/UV base,CodedData */ 175 #define RELOC_SLICE_PARAMS_PNW(dest, offset, buf) pnw_cmdbuf_add_relocation(cmdbuf, (uint32_t*)(dest), buf, offset, 0XFFFFFFFF, 0, 0, 2,(uint32_t *)cmdbuf->slice_params_p) 176 177 /* operation number is inserted by DRM */ 178 /* 179 #define pnw_cmdbuf_insert_command(cmdbuf,cmdhdr,size,hint) \ 180 do { *cmdbuf->cmd_idx++ = ((cmdhdr) << 1) | ((size)<<8) | ((hint)<<16); } while(0) 181 */ 182 183 #define pnw_cmdbuf_insert_command_param(param) \ 184 do { *cmdbuf->cmd_idx++ = param; } while(0) 185 186 187 #define pnw_cmdbuf_insert_reg_write(base, offset, value) \ 188 do { *cmdbuf->cmd_idx++ = base + offset; *cmdbuf->cmd_idx++ = value; count++; } while(0) 189 190 void pnw_cmdbuf_insert_command_package(object_context_p obj_context, 191 int32_t core, 192 uint32_t cmd_id, 193 psb_buffer_p command_data, 194 uint32_t offset); 195 196 /* 197 * Advances "obj_context" to the next cmdbuf 198 * 199 * Returns 0 on success 200 */ 201 int pnw_context_get_next_cmdbuf(object_context_p obj_context); 202 203 /* 204 * Submits the current cmdbuf 205 * 206 * Returns 0 on success 207 */ 208 int pnw_context_submit_cmdbuf(object_context_p obj_context); 209 210 /* 211 * Get a encode surface FRAMESKIP flag, and store it into frame_skip argument 212 * 213 * Returns 0 on success 214 */ 215 int pnw_surface_get_frameskip(psb_driver_data_p driver_data, psb_surface_p psb_surface, int *frame_skip); 216 217 /* 218 * Flushes the pending cmdbuf 219 * 220 * Return 0 on success 221 */ 222 int pnw_context_flush_cmdbuf(object_context_p obj_context); 223 224 /* 225 * Get the number of paralled cores used. 226 * 227 * Return the number of paralled cores used. 228 */ 229 int pnw_get_parallel_core_number(object_context_p obj_context); 230 #endif /* _PNW_CMDBUF_H_ */ 231 232
