1 /* 2 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PSCI_H__ 8 #define __PSCI_H__ 9 10 #include <bakery_lock.h> 11 #include <bl_common.h> 12 #include <platform_def.h> /* for PLAT_NUM_PWR_DOMAINS */ 13 #if ENABLE_PLAT_COMPAT 14 #include <psci_compat.h> 15 #endif 16 #include <psci_lib.h> /* To maintain compatibility for SPDs */ 17 #include <utils_def.h> 18 19 /******************************************************************************* 20 * Number of power domains whose state this PSCI implementation can track 21 ******************************************************************************/ 22 #ifdef PLAT_NUM_PWR_DOMAINS 23 #define PSCI_NUM_PWR_DOMAINS PLAT_NUM_PWR_DOMAINS 24 #else 25 #define PSCI_NUM_PWR_DOMAINS (U(2) * PLATFORM_CORE_COUNT) 26 #endif 27 28 #define PSCI_NUM_NON_CPU_PWR_DOMAINS (PSCI_NUM_PWR_DOMAINS - \ 29 PLATFORM_CORE_COUNT) 30 31 /* This is the power level corresponding to a CPU */ 32 #define PSCI_CPU_PWR_LVL (0) 33 34 /* 35 * The maximum power level supported by PSCI. Since PSCI CPU_SUSPEND 36 * uses the old power_state parameter format which has 2 bits to specify the 37 * power level, this constant is defined to be 3. 38 */ 39 #define PSCI_MAX_PWR_LVL U(3) 40 41 /******************************************************************************* 42 * Defines for runtime services function ids 43 ******************************************************************************/ 44 #define PSCI_VERSION U(0x84000000) 45 #define PSCI_CPU_SUSPEND_AARCH32 U(0x84000001) 46 #define PSCI_CPU_SUSPEND_AARCH64 U(0xc4000001) 47 #define PSCI_CPU_OFF U(0x84000002) 48 #define PSCI_CPU_ON_AARCH32 U(0x84000003) 49 #define PSCI_CPU_ON_AARCH64 U(0xc4000003) 50 #define PSCI_AFFINITY_INFO_AARCH32 U(0x84000004) 51 #define PSCI_AFFINITY_INFO_AARCH64 U(0xc4000004) 52 #define PSCI_MIG_AARCH32 U(0x84000005) 53 #define PSCI_MIG_AARCH64 U(0xc4000005) 54 #define PSCI_MIG_INFO_TYPE U(0x84000006) 55 #define PSCI_MIG_INFO_UP_CPU_AARCH32 U(0x84000007) 56 #define PSCI_MIG_INFO_UP_CPU_AARCH64 U(0xc4000007) 57 #define PSCI_SYSTEM_OFF U(0x84000008) 58 #define PSCI_SYSTEM_RESET U(0x84000009) 59 #define PSCI_FEATURES U(0x8400000A) 60 #define PSCI_NODE_HW_STATE_AARCH32 U(0x8400000d) 61 #define PSCI_NODE_HW_STATE_AARCH64 U(0xc400000d) 62 #define PSCI_SYSTEM_SUSPEND_AARCH32 U(0x8400000E) 63 #define PSCI_SYSTEM_SUSPEND_AARCH64 U(0xc400000E) 64 #define PSCI_STAT_RESIDENCY_AARCH32 U(0x84000010) 65 #define PSCI_STAT_RESIDENCY_AARCH64 U(0xc4000010) 66 #define PSCI_STAT_COUNT_AARCH32 U(0x84000011) 67 #define PSCI_STAT_COUNT_AARCH64 U(0xc4000011) 68 #define PSCI_SYSTEM_RESET2_AARCH32 U(0x84000012) 69 #define PSCI_SYSTEM_RESET2_AARCH64 U(0xc4000012) 70 #define PSCI_MEM_PROTECT U(0x84000013) 71 #define PSCI_MEM_CHK_RANGE_AARCH32 U(0x84000014) 72 #define PSCI_MEM_CHK_RANGE_AARCH64 U(0xc4000014) 73 74 /* Macro to help build the psci capabilities bitfield */ 75 #define define_psci_cap(x) (U(1) << (x & U(0x1f))) 76 77 /* 78 * Number of PSCI calls (above) implemented 79 */ 80 #if ENABLE_PSCI_STAT 81 #define PSCI_NUM_CALLS U(22) 82 #else 83 #define PSCI_NUM_CALLS U(18) 84 #endif 85 86 /* The macros below are used to identify PSCI calls from the SMC function ID */ 87 #define PSCI_FID_MASK U(0xffe0) 88 #define PSCI_FID_VALUE U(0) 89 #define is_psci_fid(_fid) \ 90 (((_fid) & PSCI_FID_MASK) == PSCI_FID_VALUE) 91 92 /******************************************************************************* 93 * PSCI Migrate and friends 94 ******************************************************************************/ 95 #define PSCI_TOS_UP_MIG_CAP U(0) 96 #define PSCI_TOS_NOT_UP_MIG_CAP U(1) 97 #define PSCI_TOS_NOT_PRESENT_MP U(2) 98 99 /******************************************************************************* 100 * PSCI CPU_SUSPEND 'power_state' parameter specific defines 101 ******************************************************************************/ 102 #define PSTATE_ID_SHIFT U(0) 103 104 #if PSCI_EXTENDED_STATE_ID 105 #define PSTATE_VALID_MASK U(0xB0000000) 106 #define PSTATE_TYPE_SHIFT U(30) 107 #define PSTATE_ID_MASK U(0xfffffff) 108 #else 109 #define PSTATE_VALID_MASK U(0xFCFE0000) 110 #define PSTATE_TYPE_SHIFT U(16) 111 #define PSTATE_PWR_LVL_SHIFT U(24) 112 #define PSTATE_ID_MASK U(0xffff) 113 #define PSTATE_PWR_LVL_MASK U(0x3) 114 115 #define psci_get_pstate_pwrlvl(pstate) (((pstate) >> PSTATE_PWR_LVL_SHIFT) & \ 116 PSTATE_PWR_LVL_MASK) 117 #define psci_make_powerstate(state_id, type, pwrlvl) \ 118 (((state_id) & PSTATE_ID_MASK) << PSTATE_ID_SHIFT) |\ 119 (((type) & PSTATE_TYPE_MASK) << PSTATE_TYPE_SHIFT) |\ 120 (((pwrlvl) & PSTATE_PWR_LVL_MASK) << PSTATE_PWR_LVL_SHIFT) 121 #endif /* __PSCI_EXTENDED_STATE_ID__ */ 122 123 #define PSTATE_TYPE_STANDBY U(0x0) 124 #define PSTATE_TYPE_POWERDOWN U(0x1) 125 #define PSTATE_TYPE_MASK U(0x1) 126 127 #define psci_get_pstate_id(pstate) (((pstate) >> PSTATE_ID_SHIFT) & \ 128 PSTATE_ID_MASK) 129 #define psci_get_pstate_type(pstate) (((pstate) >> PSTATE_TYPE_SHIFT) & \ 130 PSTATE_TYPE_MASK) 131 #define psci_check_power_state(pstate) ((pstate) & PSTATE_VALID_MASK) 132 133 /******************************************************************************* 134 * PSCI CPU_FEATURES feature flag specific defines 135 ******************************************************************************/ 136 /* Features flags for CPU SUSPEND power state parameter format. Bits [1:1] */ 137 #define FF_PSTATE_SHIFT U(1) 138 #define FF_PSTATE_ORIG U(0) 139 #define FF_PSTATE_EXTENDED U(1) 140 #if PSCI_EXTENDED_STATE_ID 141 #define FF_PSTATE FF_PSTATE_EXTENDED 142 #else 143 #define FF_PSTATE FF_PSTATE_ORIG 144 #endif 145 146 /* Features flags for CPU SUSPEND OS Initiated mode support. Bits [0:0] */ 147 #define FF_MODE_SUPPORT_SHIFT U(0) 148 #define FF_SUPPORTS_OS_INIT_MODE U(1) 149 150 /******************************************************************************* 151 * PSCI version 152 ******************************************************************************/ 153 #define PSCI_MAJOR_VER (U(1) << 16) 154 #define PSCI_MINOR_VER U(0x1) 155 156 /******************************************************************************* 157 * PSCI error codes 158 ******************************************************************************/ 159 #define PSCI_E_SUCCESS 0 160 #define PSCI_E_NOT_SUPPORTED -1 161 #define PSCI_E_INVALID_PARAMS -2 162 #define PSCI_E_DENIED -3 163 #define PSCI_E_ALREADY_ON -4 164 #define PSCI_E_ON_PENDING -5 165 #define PSCI_E_INTERN_FAIL -6 166 #define PSCI_E_NOT_PRESENT -7 167 #define PSCI_E_DISABLED -8 168 #define PSCI_E_INVALID_ADDRESS -9 169 170 #define PSCI_INVALID_MPIDR ~((u_register_t)0) 171 172 /* 173 * SYSTEM_RESET2 macros 174 */ 175 #define PSCI_RESET2_TYPE_VENDOR_SHIFT 31 176 #define PSCI_RESET2_TYPE_VENDOR (1U << PSCI_RESET2_TYPE_VENDOR_SHIFT) 177 #define PSCI_RESET2_TYPE_ARCH (0U << PSCI_RESET2_TYPE_VENDOR_SHIFT) 178 #define PSCI_RESET2_SYSTEM_WARM_RESET (PSCI_RESET2_TYPE_ARCH | 0) 179 180 #ifndef __ASSEMBLY__ 181 182 #include <stdint.h> 183 #include <types.h> 184 185 /* 186 * These are the states reported by the PSCI_AFFINITY_INFO API for the specified 187 * CPU. The definitions of these states can be found in Section 5.7.1 in the 188 * PSCI specification (ARM DEN 0022C). 189 */ 190 typedef enum { 191 AFF_STATE_ON = U(0), 192 AFF_STATE_OFF = U(1), 193 AFF_STATE_ON_PENDING = U(2) 194 } aff_info_state_t; 195 196 /* 197 * These are the power states reported by PSCI_NODE_HW_STATE API for the 198 * specified CPU. The definitions of these states can be found in Section 5.15.3 199 * of PSCI specification (ARM DEN 0022C). 200 */ 201 typedef enum { 202 HW_ON = U(0), 203 HW_OFF = U(1), 204 HW_STANDBY = U(2) 205 } node_hw_state_t; 206 207 /* 208 * Macro to represent invalid affinity level within PSCI. 209 */ 210 #define PSCI_INVALID_PWR_LVL (PLAT_MAX_PWR_LVL + U(1)) 211 212 /* 213 * Type for representing the local power state at a particular level. 214 */ 215 typedef uint8_t plat_local_state_t; 216 217 /* The local state macro used to represent RUN state. */ 218 #define PSCI_LOCAL_STATE_RUN U(0) 219 220 /* 221 * Macro to test whether the plat_local_state is RUN state 222 */ 223 #define is_local_state_run(plat_local_state) \ 224 ((plat_local_state) == PSCI_LOCAL_STATE_RUN) 225 226 /* 227 * Macro to test whether the plat_local_state is RETENTION state 228 */ 229 #define is_local_state_retn(plat_local_state) \ 230 (((plat_local_state) > PSCI_LOCAL_STATE_RUN) && \ 231 ((plat_local_state) <= PLAT_MAX_RET_STATE)) 232 233 /* 234 * Macro to test whether the plat_local_state is OFF state 235 */ 236 #define is_local_state_off(plat_local_state) \ 237 (((plat_local_state) > PLAT_MAX_RET_STATE) && \ 238 ((plat_local_state) <= PLAT_MAX_OFF_STATE)) 239 240 /***************************************************************************** 241 * This data structure defines the representation of the power state parameter 242 * for its exchange between the generic PSCI code and the platform port. For 243 * example, it is used by the platform port to specify the requested power 244 * states during a power management operation. It is used by the generic code to 245 * inform the platform about the target power states that each level should 246 * enter. 247 ****************************************************************************/ 248 typedef struct psci_power_state { 249 /* 250 * The pwr_domain_state[] stores the local power state at each level 251 * for the CPU. 252 */ 253 plat_local_state_t pwr_domain_state[PLAT_MAX_PWR_LVL + U(1)]; 254 } psci_power_state_t; 255 256 /******************************************************************************* 257 * Structure used to store per-cpu information relevant to the PSCI service. 258 * It is populated in the per-cpu data array. In return we get a guarantee that 259 * this information will not reside on a cache line shared with another cpu. 260 ******************************************************************************/ 261 typedef struct psci_cpu_data { 262 /* State as seen by PSCI Affinity Info API */ 263 aff_info_state_t aff_info_state; 264 265 /* 266 * Highest power level which takes part in a power management 267 * operation. 268 */ 269 unsigned char target_pwrlvl; 270 271 /* The local power state of this CPU */ 272 plat_local_state_t local_state; 273 } psci_cpu_data_t; 274 275 /******************************************************************************* 276 * Structure populated by platform specific code to export routines which 277 * perform common low level power management functions 278 ******************************************************************************/ 279 typedef struct plat_psci_ops { 280 void (*cpu_standby)(plat_local_state_t cpu_state); 281 int (*pwr_domain_on)(u_register_t mpidr); 282 void (*pwr_domain_off)(const psci_power_state_t *target_state); 283 void (*pwr_domain_suspend_pwrdown_early)( 284 const psci_power_state_t *target_state); 285 void (*pwr_domain_suspend)(const psci_power_state_t *target_state); 286 void (*pwr_domain_on_finish)(const psci_power_state_t *target_state); 287 void (*pwr_domain_suspend_finish)( 288 const psci_power_state_t *target_state); 289 void (*pwr_domain_pwr_down_wfi)( 290 const psci_power_state_t *target_state) __dead2; 291 void (*system_off)(void) __dead2; 292 void (*system_reset)(void) __dead2; 293 int (*validate_power_state)(unsigned int power_state, 294 psci_power_state_t *req_state); 295 int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint); 296 void (*get_sys_suspend_power_state)( 297 psci_power_state_t *req_state); 298 int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state, 299 int pwrlvl); 300 int (*translate_power_state_by_mpidr)(u_register_t mpidr, 301 unsigned int power_state, 302 psci_power_state_t *output_state); 303 int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level); 304 int (*mem_protect_chk)(uintptr_t base, u_register_t length); 305 int (*read_mem_protect)(int *val); 306 int (*write_mem_protect)(int val); 307 int (*system_reset2)(int is_vendor, 308 int reset_type, u_register_t cookie); 309 } plat_psci_ops_t; 310 311 /******************************************************************************* 312 * Function & Data prototypes 313 ******************************************************************************/ 314 unsigned int psci_version(void); 315 int psci_cpu_on(u_register_t target_cpu, 316 uintptr_t entrypoint, 317 u_register_t context_id); 318 int psci_cpu_suspend(unsigned int power_state, 319 uintptr_t entrypoint, 320 u_register_t context_id); 321 int psci_system_suspend(uintptr_t entrypoint, u_register_t context_id); 322 int psci_cpu_off(void); 323 int psci_affinity_info(u_register_t target_affinity, 324 unsigned int lowest_affinity_level); 325 int psci_migrate(u_register_t target_cpu); 326 int psci_migrate_info_type(void); 327 long psci_migrate_info_up_cpu(void); 328 int psci_node_hw_state(u_register_t target_cpu, 329 unsigned int power_level); 330 int psci_features(unsigned int psci_fid); 331 void __dead2 psci_power_down_wfi(void); 332 void psci_arch_setup(void); 333 334 /* 335 * The below API is deprecated. This is now replaced by bl31_warmboot_entry in 336 * AArch64. 337 */ 338 void psci_entrypoint(void) __deprecated; 339 340 #endif /*__ASSEMBLY__*/ 341 342 #endif /* __PSCI_H__ */ 343
