| /external/clang/lib/Rewrite/ |
| HTMLRewrite.cpp | 57 void html::HighlightRange(RewriteBuffer &RB, unsigned B, unsigned E,
61 RB.InsertTextAfter(B, StartTag);
62 RB.InsertTextBefore(E, EndTag);
76 RB.InsertTextBefore(LastNonWhiteSpace+1, EndTag);
95 RB.InsertTextAfter(i, StartTag);
115 RewriteBuffer &RB = R.getEditBuffer(FID);
128 RB.ReplaceText(FilePos, 1, " ");
132 RB.ReplaceText(FilePos, 1, "<hr>");
141 RB.ReplaceText(FilePos, 1,
145 RB.ReplaceText(FilePos, 1, StringRef(" ", NumSpaces))
[all...] |
| Rewriter.cpp | 143 const RewriteBuffer &RB = I->second;
144 EndOff = RB.getMappedOffset(EndOff, opts.IncludeInsertsAtEndOfRange);
145 StartOff = RB.getMappedOffset(StartOff, !opts.IncludeInsertsAtBeginOfRange);
195 const RewriteBuffer &RB = I->second;
196 EndOff = RB.getMappedOffset(EndOff, true);
197 StartOff = RB.getMappedOffset(StartOff);
204 RewriteBuffer::iterator Start = RB.begin();
381 RewriteBuffer &RB = getEditBuffer(FID);
389 RB.InsertText(offs, indent, /*InsertAfter=*/false);
|
| /external/clang/test/Layout/ |
| ms-x86-alias-avoidance-padding.cpp | 302 struct RB { char c; };
306 struct RX0 : RB, RA {};
307 struct RX1 : RA, RB {};
309 struct RX3 : RA { RB a; };
311 struct RX5 { RA a; RB b; };
312 struct RX6 : virtual RV { RB a; };
324 // CHECK-NEXT: 0 | struct RB (base)
337 // CHECK-X64-NEXT: 0 | struct RB (base)
350 // CHECK-NEXT: 0 | struct RB (base)
360 // CHECK-X64-NEXT: 0 | struct RB (base
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| RegisterBankInfo.cpp | 70 RegisterBank &RB = getRegBank(ID);
73 DEBUG(dbgs() << "Add coverage for: " << RB << '\n');
75 // Check if RB is underconstruction.
76 if (!RB.isValid())
77 RB.ContainedRegClasses.resize(NbOfRegClasses);
78 else if (RB.covers(*TRI.getRegClass(RCId)))
79 // If RB already covers this register class, there is nothing
83 BitVector &Covered = RB.ContainedRegClasses;
89 unsigned &MaxSize = RB.Size;
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/Disassembler/ |
| MBlazeDisassembler.cpp | 527 unsigned RB = getRB(insn);
536 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
539 instr.addOperand(MCOperand::CreateReg(RB));
544 if (RD == UNSUPPORTED || RA == UNSUPPORTED || RB == UNSUPPORTED)
548 instr.addOperand(MCOperand::CreateReg(RB));
595 if (RA == UNSUPPORTED || RB == UNSUPPORTED)
598 instr.addOperand(MCOperand::CreateReg(RB));
609 if (RD == UNSUPPORTED || RB == UNSUPPORTED)
612 instr.addOperand(MCOperand::CreateReg(RB));
623 if (RB == UNSUPPORTED
[all...] |
| /toolchain/binutils/binutils-2.27/opcodes/ |
| rl78-decode.c | 62 #define RB(x) ((x)+RL78_Reg_X)
110 #define DRB(r) OP (0, RL78_Operand_Register, RB(r), 0)
121 #define SRB(r) OP (1, RL78_Operand_Register, RB(r), 0)
[all...] |
| alpha-opc.c | 57 /* The RB field when it is the same as the RA field in the same insn.
59 the RA field into the RB field, and the extraction function just
210 #define RB (RA + 1)
212 #define RC (RB + 1)
231 /* The RB field when it needs parentheses. */
235 /* The RB field when it needs parentheses _and_ a preceding comma. */
240 /* The RB field when it must be the same as the RA field. */
244 /* The RC field when it must be the same as the RB field. */
253 /* The RC field when it can *default* to RB. */
263 /* The FC field when it can *default* to RB. *
[all...] |
| nds32-asm.c | 102 {"rb", 10, 5, 0, HW_GPR, NULL},
219 #define RB(r) (r << 10)
292 {"jr", "%rb", JREG (JR), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
293 {"jral", "%rt,%rb", JREG (JRAL), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
294 {"jrnez", "%rb", JREG (JRNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
295 {"jralnez", "%rt,%rb", JREG (JRALNEZ), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
296 {"ret", "%rb", JREG (JR) | JREG_RET, 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
298 {"jral", "%rb", JREG (JRAL) | RT (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL},
299 {"jralnez", "%rb", JREG (JRALNEZ) | RT (30), 4, ATTR (BRANCH) | ATTR_V3, 0, NULL, 0, NULL},
300 {"ret", "", JREG (JR) | JREG_RET | RB (30), 4, ATTR (BRANCH) | ATTR_ALL, 0, NULL, 0, NULL}
[all...] |
| arc-opc.c | 33 /* Insert RB register into a 32-bit opcode. */
[all...] |
| ppc-opc.c | 548 /* The RB field in an X, XO, M, or MDS form instruction. */
549 #define RB RAOPT + 1
553 /* The RB field in an X form instruction when it must be the same as
556 #define RBS RB + 1
559 /* The RB field in an lswx instruction, which has special value
564 /* The RB field of the dccci and iccci instructions, which are optional. */
[all...] |
| /device/linaro/bootloader/edk2/AppPkg/Applications/Lua/src/ |
| lvm.c | 335 void luaV_objlen (lua_State *L, StkId ra, const TValue *rb) {
337 switch (ttypenv(rb)) {
339 Table *h = hvalue(rb);
346 setnvalue(ra, cast_num(tsvalue(rb)->len));
350 tm = luaT_gettmbyobj(L, rb, TM_LEN);
352 luaG_typeerror(L, rb, "get length of");
356 callTM(L, tm, rb, rb, ra, 1);
360 void luaV_arith (lua_State *L, StkId ra, const TValue *rb,
364 if ((b = luaV_tonumber(rb, &tempb)) != NULL &
[all...] |
| /external/skia/gm/ |
| image.cpp | 93 RB = W * 4 + 8,
97 fBufferSize = RB * H;
153 sk_sp<SkSurface> surf0(SkSurface::MakeRasterDirect(info, fBuffer, RB));
|
| /external/skqp/gm/ |
| image.cpp | 92 RB = W * 4 + 8,
96 fBufferSize = RB * H;
152 sk_sp<SkSurface> surf0(SkSurface::MakeRasterDirect(info, fBuffer, RB));
|
| /external/syslinux/com32/lua/src/ |
| lvm.c | 358 void luaV_objlen (lua_State *L, StkId ra, const TValue *rb) {
360 switch (ttypenv(rb)) {
362 Table *h = hvalue(rb);
369 setnvalue(ra, cast_num(tsvalue(rb)->len));
373 tm = luaT_gettmbyobj(L, rb, TM_LEN);
375 luaG_typeerror(L, rb, "get length of");
379 callTM(L, tm, rb, rb, ra, 1);
383 void luaV_arith (lua_State *L, StkId ra, const TValue *rb,
387 if ((b = luaV_tonumber(rb, &tempb)) != NULL &
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonVLIWPacketizer.cpp | 221 MachineBasicBlock::iterator RB = Begin;
222 while (RB != End && HII->isSchedulingBoundary(*RB, &MB, MF))
223 ++RB;
226 MachineBasicBlock::iterator RE = RB;
232 // If RB == End, then RE == End.
233 if (RB != End)
234 Packetizer.PacketizeMIs(&MB, RB, RE);
[all...] |
| HexagonHardwareLoops.cpp | [all...] |
| /libcore/luni/src/test/java/libcore/java/util/ |
| EnumSetTest.java | 103 FE, CO, NI, CU, ZN, GA, GE, AS, SE, BR, KR, RB, SR, Y, ZR, NB, MO, TC, RU, RH, PD, AG, CD,
|
| /external/clang/lib/Basic/ |
| SourceManager.cpp | [all...] |
| /external/valgrind/VEX/priv/ |
| guest_ppc_toIR.c | 370 /* Extract RB (2nd source register) field, instr[15:11] */
[all...] |
| /prebuilts/misc/common/robolectric/3.1.1/lib/ |
| nekohtml-1.9.6.2.jar | |
| vtd-xml-2.11.jar | |
| /prebuilts/tools/common/m2/repository/nekohtml/nekohtml/1.9.6.2/ |
| nekohtml-1.9.6.2.jar | |
| /prebuilts/tools/common/m2/repository/net/sourceforge/nekohtml/nekohtml/1.9.16/ |
| nekohtml-1.9.16.jar | |
| /prebuilts/tools/common/m2/repository/net/sourceforge/nekohtml/nekohtml/1.9.20/ |
| nekohtml-1.9.20.jar | |
| /external/robolectric/v3/libs/ |
| vtd-xml-2.11.jar | |
