1 /** @file 2 * 3 * Copyright (c) 2014-2017, Linaro Limited. All rights reserved. 4 * 5 * This program and the accompanying materials 6 * are licensed and made available under the terms and conditions of the BSD License 7 * which accompanies this distribution. The full text of the license may be found at 8 * http://opensource.org/licenses/bsd-license.php 9 * 10 * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 12 * 13 **/ 14 15 #ifndef __HI6220_H__ 16 #define __HI6220_H__ 17 18 /*********************************************************************************** 19 // Platform Memory Map 20 ************************************************************************************/ 21 22 // SOC peripherals (UART, I2C, I2S, USB, etc) 23 #define HI6220_PERIPH_BASE 0xF4000000 24 #define HI6220_PERIPH_SZ 0x05800000 25 26 #define PERI_CTRL_BASE 0xF7030000 27 #define SC_PERIPH_CTRL4 0x00C 28 #define CTRL4_FPGA_EXT_PHY_SEL BIT3 29 #define CTRL4_PICO_SIDDQ BIT6 30 #define CTRL4_PICO_OGDISABLE BIT8 31 #define CTRL4_PICO_VBUSVLDEXT BIT10 32 #define CTRL4_PICO_VBUSVLDEXTSEL BIT11 33 #define CTRL4_OTG_PHY_SEL BIT21 34 35 #define SC_PERIPH_CTRL5 0x010 36 37 #define CTRL5_USBOTG_RES_SEL BIT3 38 #define CTRL5_PICOPHY_ACAENB BIT4 39 #define CTRL5_PICOPHY_BC_MODE BIT5 40 #define CTRL5_PICOPHY_CHRGSEL BIT6 41 #define CTRL5_PICOPHY_VDATSRCEND BIT7 42 #define CTRL5_PICOPHY_VDATDETENB BIT8 43 #define CTRL5_PICOPHY_DCDENB BIT9 44 #define CTRL5_PICOPHY_IDDIG BIT10 45 46 #define SC_PERIPH_CTRL8 0x018 47 #define SC_PERIPH_CLKEN0 0x200 48 #define SC_PERIPH_CLKDIS0 0x204 49 #define SC_PERIPH_CLKSTAT0 0x208 50 51 #define SC_PERIPH_CLKEN3 0x230 52 #define SC_PERIPH_RSTEN3 0x330 53 #define SC_PERIPH_RSTEN0 0x300 54 #define SC_PERIPH_RSTDIS0 0x304 55 #define SC_PERIPH_RSTSTAT0 0x308 56 #define SC_PERIPH_RSTDIS3 0x334 57 #define SC_PERIPH_RSTSTAT3 0x338 58 59 #define RST0_USBOTG_BUS BIT4 60 #define RST0_POR_PICOPHY BIT5 61 #define RST0_USBOTG BIT6 62 #define RST0_USBOTG_32K BIT7 63 64 /* SC_PERIPH_RSTEN0/RSTDIS0/RSTSTAT0 */ 65 #define PERIPH_RST0_MMC2 (1 << 2) 66 67 /* SC_PERIPH_RSTEN3/RSTDIS3/RSTSTAT3 */ 68 #define PERIPH_RST3_CSSYS (1 << 0) 69 #define PERIPH_RST3_I2C0 (1 << 1) 70 #define PERIPH_RST3_I2C1 (1 << 2) 71 #define PERIPH_RST3_I2C2 (1 << 3) 72 #define PERIPH_RST3_I2C3 (1 << 4) 73 #define PERIPH_RST3_UART1 (1 << 5) 74 #define PERIPH_RST3_UART2 (1 << 6) 75 #define PERIPH_RST3_UART3 (1 << 7) 76 #define PERIPH_RST3_UART4 (1 << 8) 77 #define PERIPH_RST3_SSP (1 << 9) 78 #define PERIPH_RST3_PWM (1 << 10) 79 #define PERIPH_RST3_BLPWM (1 << 11) 80 #define PERIPH_RST3_TSENSOR (1 << 12) 81 #define PERIPH_RST3_DAPB (1 << 18) 82 #define PERIPH_RST3_HKADC (1 << 19) 83 #define PERIPH_RST3_CODEC_SSI (1 << 20) 84 #define PERIPH_RST3_PMUSSI1 (1 << 22) 85 86 #define EYE_PATTERN_PARA 0x7053348c 87 88 #define MDDRC_AXI_BASE 0xF7120000 89 #define AXI_REGION_MAP 0x100 90 #define HIKEY_REGION_SIZE_MASK (7 << 8) 91 // (0 << 8) means 16MB, (7 << 8) means 2GB 92 #define HIKEY_REGION_SIZE(x) (1U << ((((x) & HIKEY_REGION_SIZE_MASK) >> 8) + 24)) 93 94 #define AO_CTRL_BASE 0xF7800000 95 #define SC_PW_MTCMOS_EN0 0x830 96 #define SC_PW_MTCMOS_DIS0 0x834 97 #define SC_PW_MTCMOS_STAT0 0x838 98 #define SC_PW_MTCMOS_ACK_STAT0 0x83c 99 #define PW_EN0_G3D (1 << 1) 100 101 #define PMUSSI_BASE 0xF8000000 102 103 #define PMUSSI_REG(x) (PMUSSI_BASE + ((x) << 2)) 104 105 106 #endif /* __HI6220_H__ */ 107
