1 /** @file 2 Lib function for Pei Quark South Cluster. 3 4 Copyright (c) 2013-2016 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 #include "CommonHeader.h" 16 17 /** 18 Program SVID/SID the same as VID/DID* 19 **/ 20 EFI_STATUS 21 EFIAPI 22 InitializeIohSsvidSsid ( 23 IN UINT8 Bus, 24 IN UINT8 Device, 25 IN UINT8 Func 26 ) 27 { 28 UINTN Index; 29 30 for (Index = 0; Index <= IOH_PCI_IOSF2AHB_0_MAX_FUNCS; Index++) { 31 if (((Device == IOH_PCI_IOSF2AHB_1_DEV_NUM) && (Index >= IOH_PCI_IOSF2AHB_1_MAX_FUNCS))) { 32 continue; 33 } 34 35 IohMmPci32(0, Bus, Device, Index, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, Index, PCI_REG_VID); 36 } 37 38 return EFI_SUCCESS; 39 } 40 41 /* Enable memory, io, and bus master for USB controller */ 42 VOID 43 EFIAPI 44 EnableUsbMemIoBusMaster ( 45 IN UINT8 UsbBusNumber 46 ) 47 { 48 UINT16 CmdReg; 49 50 CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD)); 51 CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER); 52 PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg); 53 54 CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD)); 55 CmdReg = (UINT16) (CmdReg | EFI_PCI_COMMAND_MEMORY_SPACE | EFI_PCI_COMMAND_IO_SPACE | EFI_PCI_COMMAND_BUS_MASTER); 56 PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg); 57 } 58 59 /** 60 Read south cluster GPIO input from Port A. 61 62 **/ 63 UINT32 64 EFIAPI 65 ReadIohGpioValues ( 66 VOID 67 ) 68 { 69 UINT32 GipData; 70 UINT32 GipAddr; 71 UINT32 TempBarAddr; 72 UINT16 SaveCmdReg; 73 UINT32 SaveBarReg; 74 75 TempBarAddr = (UINT32) PcdGet64(PcdIohGpioMmioBase); 76 77 GipAddr = PCI_LIB_ADDRESS( 78 PcdGet8 (PcdIohGpioBusNumber), 79 PcdGet8 (PcdIohGpioDevNumber), 80 PcdGet8 (PcdIohGpioFunctionNumber), 0); 81 82 // 83 // Save current settings for PCI CMD/BAR registers. 84 // 85 SaveCmdReg = PciRead16 (GipAddr + PCI_COMMAND_OFFSET); 86 SaveBarReg = PciRead32 (GipAddr + PcdGet8 (PcdIohGpioBarRegister)); 87 88 DEBUG ((EFI_D_INFO, "SC GPIO temporary enable at %08X\n", TempBarAddr)); 89 90 // Use predefined temporary memory resource. 91 PciWrite32 ( GipAddr + PcdGet8 (PcdIohGpioBarRegister), TempBarAddr); 92 PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE); 93 94 // Read GPIO configuration 95 GipData = MmioRead32(TempBarAddr + GPIO_EXT_PORTA); 96 97 // 98 // Restore settings for PCI CMD/BAR registers. 99 // 100 PciWrite32 ((GipAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg); 101 PciWrite16 (GipAddr + PCI_COMMAND_OFFSET, SaveCmdReg); 102 103 // Only 8 bits valid. 104 return GipData & 0x000000FF; 105 } 106
