1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ 8 #define __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ 9 10 /************************************************** 11 * sgrf reg, offset 12 **************************************************/ 13 #define SGRF_SOC_CON0_1(n) (0xc000 + (n) * 4) 14 #define SGRF_SOC_CON3_7(n) (0xe00c + ((n) - 3) * 4) 15 #define SGRF_SOC_CON8_15(n) (0x8020 + ((n) - 8) * 4) 16 #define SGRF_SOC_CON(n) (n < 3 ? SGRF_SOC_CON0_1(n) :\ 17 (n < 8 ? SGRF_SOC_CON3_7(n) :\ 18 SGRF_SOC_CON8_15(n))) 19 20 #define SGRF_PMU_SLV_CON0_1(n) (0xc240 + ((n) - 0) * 4) 21 #define SGRF_SLV_SECURE_CON0_4(n) (0xe3c0 + ((n) - 0) * 4) 22 #define SGRF_DDRRGN_CON0_16(n) ((n) * 4) 23 #define SGRF_DDRRGN_CON20_34(n) (0x50 + ((n) - 20) * 4) 24 25 /* All of master in ns */ 26 #define SGRF_SOC_ALLMST_NS 0xffff 27 28 /* security config for slave */ 29 #define SGRF_SLV_S_WMSK 0xffff0000 30 #define SGRF_SLV_S_ALL_NS 0x0 31 32 /* security config pmu slave ip */ 33 /* All of slaves is ns */ 34 #define SGRF_PMU_SLV_S_NS BIT_WITH_WMSK(0) 35 /* slaves secure attr is configed */ 36 #define SGRF_PMU_SLV_S_CFGED WMSK_BIT(0) 37 #define SGRF_PMU_SLV_CRYPTO1_NS WMSK_BIT(1) 38 39 #define SGRF_PMUSRAM_S BIT(8) 40 41 #define SGRF_INTSRAM_S BIT(13) 42 43 /* ddr region */ 44 #define SGRF_DDR_RGN_0_16_WMSK 0x0fff /* DDR RGN 0~16 size mask */ 45 46 #define SGRF_DDR_RGN_DPLL_CLK BIT_WITH_WMSK(15) /* DDR PLL output clock */ 47 #define SGRF_DDR_RGN_RTC_CLK BIT_WITH_WMSK(14) /* 32K clock for DDR PLL */ 48 49 /* All security of the DDR RGNs are bypass */ 50 #define SGRF_DDR_RGN_BYPS BIT_WITH_WMSK(9) 51 /* All security of the DDR RGNs are not bypass */ 52 #define SGRF_DDR_RGN_NO_BYPS WMSK_BIT(9) 53 54 /* The MST access the ddr rgn n with secure attribution */ 55 #define SGRF_L_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n)) 56 /* bits[16:8]*/ 57 #define SGRF_H_MST_S_DDR_RGN(n) BIT_WITH_WMSK((n) + 8) 58 59 #define SGRF_PMU_CON0 0x0c100 60 #define SGRF_PMU_CON(n) (SGRF_PMU_CON0 + (n) * 4) 61 62 /************************************************** 63 * secure timer 64 **************************************************/ 65 /* chanal0~5 */ 66 #define STIMER0_CHN_BASE(n) (STIME_BASE + 0x20 * (n)) 67 /* chanal6~11 */ 68 #define STIMER1_CHN_BASE(n) (STIME_BASE + 0x8000 + 0x20 * (n)) 69 70 /* low 32 bits */ 71 #define TIMER_END_COUNT0 0x00 72 /* high 32 bits */ 73 #define TIMER_END_COUNT1 0x04 74 75 #define TIMER_CURRENT_VALUE0 0x08 76 #define TIMER_CURRENT_VALUE1 0x0C 77 78 /* low 32 bits */ 79 #define TIMER_INIT_COUNT0 0x10 80 /* high 32 bits */ 81 #define TIMER_INIT_COUNT1 0x14 82 83 #define TIMER_INTSTATUS 0x18 84 #define TIMER_CONTROL_REG 0x1c 85 86 #define TIMER_EN 0x1 87 88 #define TIMER_FMODE (0x0 << 1) 89 #define TIMER_RMODE (0x1 << 1) 90 91 /************************************************** 92 * secure WDT 93 **************************************************/ 94 #define PCLK_WDT_CA53_GATE_SHIFT 8 95 #define PCLK_WDT_CM0_GATE_SHIFT 10 96 97 /* export secure operating APIs */ 98 void secure_watchdog_disable(void); 99 void secure_watchdog_enable(void); 100 void secure_timer_init(void); 101 void secure_sgrf_init(void); 102 void secure_sgrf_ddr_rgn_init(void); 103 __pmusramfunc void sram_secure_timer_init(void); 104 105 #endif /* __PLAT_ROCKCHIP_RK3399_DRIVER_SECURE_H__ */ 106
