1 /** @file 2 IA32/x64 architecture specific defintions needed by debug transfer protocol.It is only 3 intended to be used by Debug related module implementation. 4 5 Copyright (c) 2010 - 2012, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php. 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef __PROCESSOR_CONTEXT_H__ 17 #define __PROCESSOR_CONTEXT_H__ 18 19 // 20 // IA-32/x64 processor register index table 21 // 22 #define SOFT_DEBUGGER_REGISTER_DR0 0x00 23 #define SOFT_DEBUGGER_REGISTER_DR1 0x01 24 #define SOFT_DEBUGGER_REGISTER_DR2 0x02 25 #define SOFT_DEBUGGER_REGISTER_DR3 0x03 26 #define SOFT_DEBUGGER_REGISTER_DR6 0x04 27 #define SOFT_DEBUGGER_REGISTER_DR7 0x05 28 #define SOFT_DEBUGGER_REGISTER_EFLAGS 0x06 29 #define SOFT_DEBUGGER_REGISTER_LDTR 0x07 30 #define SOFT_DEBUGGER_REGISTER_TR 0x08 31 #define SOFT_DEBUGGER_REGISTER_GDTR0 0x09 // the low 32bit of GDTR 32 #define SOFT_DEBUGGER_REGISTER_GDTR1 0x0A // the high 32bit of GDTR 33 #define SOFT_DEBUGGER_REGISTER_IDTR0 0x0B // the low 32bit of IDTR 34 #define SOFT_DEBUGGER_REGISTER_IDTR1 0x0C // the high 32bot of IDTR 35 #define SOFT_DEBUGGER_REGISTER_EIP 0x0D 36 #define SOFT_DEBUGGER_REGISTER_GS 0x0E 37 #define SOFT_DEBUGGER_REGISTER_FS 0x0F 38 #define SOFT_DEBUGGER_REGISTER_ES 0x10 39 #define SOFT_DEBUGGER_REGISTER_DS 0x11 40 #define SOFT_DEBUGGER_REGISTER_CS 0x12 41 #define SOFT_DEBUGGER_REGISTER_SS 0x13 42 #define SOFT_DEBUGGER_REGISTER_CR0 0x14 43 #define SOFT_DEBUGGER_REGISTER_CR1 0x15 44 #define SOFT_DEBUGGER_REGISTER_CR2 0x16 45 #define SOFT_DEBUGGER_REGISTER_CR3 0x17 46 #define SOFT_DEBUGGER_REGISTER_CR4 0x18 47 48 #define SOFT_DEBUGGER_REGISTER_DI 0x19 49 #define SOFT_DEBUGGER_REGISTER_SI 0x1A 50 #define SOFT_DEBUGGER_REGISTER_BP 0x1B 51 #define SOFT_DEBUGGER_REGISTER_SP 0x1C 52 #define SOFT_DEBUGGER_REGISTER_DX 0x1D 53 #define SOFT_DEBUGGER_REGISTER_CX 0x1E 54 #define SOFT_DEBUGGER_REGISTER_BX 0x1F 55 #define SOFT_DEBUGGER_REGISTER_AX 0x20 56 57 // 58 // This below registers are only available for x64 (not valid for Ia32 mode) 59 // 60 #define SOFT_DEBUGGER_REGISTER_CR8 0x21 61 #define SOFT_DEBUGGER_REGISTER_R8 0x22 62 #define SOFT_DEBUGGER_REGISTER_R9 0x23 63 #define SOFT_DEBUGGER_REGISTER_R10 0x24 64 #define SOFT_DEBUGGER_REGISTER_R11 0x25 65 #define SOFT_DEBUGGER_REGISTER_R12 0x26 66 #define SOFT_DEBUGGER_REGISTER_R13 0x27 67 #define SOFT_DEBUGGER_REGISTER_R14 0x28 68 #define SOFT_DEBUGGER_REGISTER_R15 0x29 69 70 // 71 // This below registers are FP / MMX / XMM registers 72 // 73 #define SOFT_DEBUGGER_REGISTER_FP_BASE 0x30 74 75 #define SOFT_DEBUGGER_REGISTER_FP_FCW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x00) 76 #define SOFT_DEBUGGER_REGISTER_FP_FSW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x01) 77 #define SOFT_DEBUGGER_REGISTER_FP_FTW (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x02) 78 #define SOFT_DEBUGGER_REGISTER_FP_OPCODE (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x03) 79 #define SOFT_DEBUGGER_REGISTER_FP_EIP (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x04) 80 #define SOFT_DEBUGGER_REGISTER_FP_CS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x05) 81 #define SOFT_DEBUGGER_REGISTER_FP_DATAOFFSET (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x06) 82 #define SOFT_DEBUGGER_REGISTER_FP_DS (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x07) 83 #define SOFT_DEBUGGER_REGISTER_FP_MXCSR (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x08) 84 #define SOFT_DEBUGGER_REGISTER_FP_MXCSR_MASK (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x09) 85 #define SOFT_DEBUGGER_REGISTER_ST0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0A) 86 #define SOFT_DEBUGGER_REGISTER_ST1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0B) 87 #define SOFT_DEBUGGER_REGISTER_ST2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0C) 88 #define SOFT_DEBUGGER_REGISTER_ST3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0D) 89 #define SOFT_DEBUGGER_REGISTER_ST4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0E) 90 #define SOFT_DEBUGGER_REGISTER_ST5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x0F) 91 #define SOFT_DEBUGGER_REGISTER_ST6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x10) 92 #define SOFT_DEBUGGER_REGISTER_ST7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x11) 93 #define SOFT_DEBUGGER_REGISTER_XMM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x12) 94 #define SOFT_DEBUGGER_REGISTER_XMM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x13) 95 #define SOFT_DEBUGGER_REGISTER_XMM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x14) 96 #define SOFT_DEBUGGER_REGISTER_XMM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x15) 97 #define SOFT_DEBUGGER_REGISTER_XMM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x16) 98 #define SOFT_DEBUGGER_REGISTER_XMM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x17) 99 #define SOFT_DEBUGGER_REGISTER_XMM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x18) 100 #define SOFT_DEBUGGER_REGISTER_XMM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x19) 101 #define SOFT_DEBUGGER_REGISTER_XMM8 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1A) 102 #define SOFT_DEBUGGER_REGISTER_XMM9 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1B) 103 #define SOFT_DEBUGGER_REGISTER_XMM10 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1C) 104 #define SOFT_DEBUGGER_REGISTER_XMM11 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1D) 105 #define SOFT_DEBUGGER_REGISTER_XMM12 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1E) 106 #define SOFT_DEBUGGER_REGISTER_XMM13 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x1F) 107 #define SOFT_DEBUGGER_REGISTER_XMM14 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x20) 108 #define SOFT_DEBUGGER_REGISTER_XMM15 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x21) 109 #define SOFT_DEBUGGER_REGISTER_MM0 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x22) 110 #define SOFT_DEBUGGER_REGISTER_MM1 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x23) 111 #define SOFT_DEBUGGER_REGISTER_MM2 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x24) 112 #define SOFT_DEBUGGER_REGISTER_MM3 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x25) 113 #define SOFT_DEBUGGER_REGISTER_MM4 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x26) 114 #define SOFT_DEBUGGER_REGISTER_MM5 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x27) 115 #define SOFT_DEBUGGER_REGISTER_MM6 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x28) 116 #define SOFT_DEBUGGER_REGISTER_MM7 (SOFT_DEBUGGER_REGISTER_FP_BASE + 0x29) 117 118 #define SOFT_DEBUGGER_REGISTER_MAX SOFT_DEBUGGER_REGISTER_MM7 119 120 #define SOFT_DEBUGGER_MSR_EFER (0xC0000080) 121 122 #pragma pack(1) 123 124 /// 125 /// FXSAVE_STATE 126 /// FP / MMX / XMM registers (see fxrstor instruction definition) 127 /// 128 typedef struct { 129 UINT16 Fcw; 130 UINT16 Fsw; 131 UINT16 Ftw; 132 UINT16 Opcode; 133 UINT32 Eip; 134 UINT16 Cs; 135 UINT16 Reserved1; 136 UINT32 DataOffset; 137 UINT16 Ds; 138 UINT8 Reserved2[2]; 139 UINT32 Mxcsr; 140 UINT32 Mxcsr_Mask; 141 UINT8 St0Mm0[10]; 142 UINT8 Reserved3[6]; 143 UINT8 St1Mm1[10]; 144 UINT8 Reserved4[6]; 145 UINT8 St2Mm2[10]; 146 UINT8 Reserved5[6]; 147 UINT8 St3Mm3[10]; 148 UINT8 Reserved6[6]; 149 UINT8 St4Mm4[10]; 150 UINT8 Reserved7[6]; 151 UINT8 St5Mm5[10]; 152 UINT8 Reserved8[6]; 153 UINT8 St6Mm6[10]; 154 UINT8 Reserved9[6]; 155 UINT8 St7Mm7[10]; 156 UINT8 Reserved10[6]; 157 UINT8 Xmm0[16]; 158 UINT8 Xmm1[16]; 159 UINT8 Xmm2[16]; 160 UINT8 Xmm3[16]; 161 UINT8 Xmm4[16]; 162 UINT8 Xmm5[16]; 163 UINT8 Xmm6[16]; 164 UINT8 Xmm7[16]; 165 UINT8 Reserved11[14 * 16]; 166 } DEBUG_DATA_IA32_FX_SAVE_STATE; 167 168 /// 169 /// IA-32 processor context definition 170 /// 171 typedef struct { 172 UINT32 ExceptionData; 173 DEBUG_DATA_IA32_FX_SAVE_STATE FxSaveState; 174 UINT32 Dr0; 175 UINT32 Dr1; 176 UINT32 Dr2; 177 UINT32 Dr3; 178 UINT32 Dr6; 179 UINT32 Dr7; 180 UINT32 Eflags; 181 UINT32 Ldtr; 182 UINT32 Tr; 183 UINT32 Gdtr[2]; 184 UINT32 Idtr[2]; 185 UINT32 Eip; 186 UINT32 Gs; 187 UINT32 Fs; 188 UINT32 Es; 189 UINT32 Ds; 190 UINT32 Cs; 191 UINT32 Ss; 192 UINT32 Cr0; 193 UINT32 Cr1; ///< Reserved 194 UINT32 Cr2; 195 UINT32 Cr3; 196 UINT32 Cr4; 197 UINT32 Edi; 198 UINT32 Esi; 199 UINT32 Ebp; 200 UINT32 Esp; 201 UINT32 Edx; 202 UINT32 Ecx; 203 UINT32 Ebx; 204 UINT32 Eax; 205 } DEBUG_DATA_IA32_SYSTEM_CONTEXT; 206 207 /// 208 /// FXSAVE_STATE 209 /// FP / MMX / XMM registers (see fxrstor instruction definition) 210 /// 211 typedef struct { 212 UINT16 Fcw; 213 UINT16 Fsw; 214 UINT16 Ftw; 215 UINT16 Opcode; 216 UINT32 Eip; 217 UINT16 Cs; 218 UINT16 Reserved1; 219 UINT32 DataOffset; 220 UINT16 Ds; 221 UINT8 Reserved2[2]; 222 UINT32 Mxcsr; 223 UINT32 Mxcsr_Mask; 224 UINT8 St0Mm0[10]; 225 UINT8 Reserved3[6]; 226 UINT8 St1Mm1[10]; 227 UINT8 Reserved4[6]; 228 UINT8 St2Mm2[10]; 229 UINT8 Reserved5[6]; 230 UINT8 St3Mm3[10]; 231 UINT8 Reserved6[6]; 232 UINT8 St4Mm4[10]; 233 UINT8 Reserved7[6]; 234 UINT8 St5Mm5[10]; 235 UINT8 Reserved8[6]; 236 UINT8 St6Mm6[10]; 237 UINT8 Reserved9[6]; 238 UINT8 St7Mm7[10]; 239 UINT8 Reserved10[6]; 240 UINT8 Xmm0[16]; 241 UINT8 Xmm1[16]; 242 UINT8 Xmm2[16]; 243 UINT8 Xmm3[16]; 244 UINT8 Xmm4[16]; 245 UINT8 Xmm5[16]; 246 UINT8 Xmm6[16]; 247 UINT8 Xmm7[16]; 248 UINT8 Xmm8[16]; 249 UINT8 Xmm9[16]; 250 UINT8 Xmm10[16]; 251 UINT8 Xmm11[16]; 252 UINT8 Xmm12[16]; 253 UINT8 Xmm13[16]; 254 UINT8 Xmm14[16]; 255 UINT8 Xmm15[16]; 256 UINT8 Reserved11[6 * 16]; 257 } DEBUG_DATA_X64_FX_SAVE_STATE; 258 259 /// 260 /// x64 processor context definition 261 /// 262 typedef struct { 263 UINT64 ExceptionData; 264 DEBUG_DATA_X64_FX_SAVE_STATE FxSaveState; 265 UINT64 Dr0; 266 UINT64 Dr1; 267 UINT64 Dr2; 268 UINT64 Dr3; 269 UINT64 Dr6; 270 UINT64 Dr7; 271 UINT64 Eflags; 272 UINT64 Ldtr; 273 UINT64 Tr; 274 UINT64 Gdtr[2]; 275 UINT64 Idtr[2]; 276 UINT64 Eip; 277 UINT64 Gs; 278 UINT64 Fs; 279 UINT64 Es; 280 UINT64 Ds; 281 UINT64 Cs; 282 UINT64 Ss; 283 UINT64 Cr0; 284 UINT64 Cr1; ///< Reserved 285 UINT64 Cr2; 286 UINT64 Cr3; 287 UINT64 Cr4; 288 UINT64 Rdi; 289 UINT64 Rsi; 290 UINT64 Rbp; 291 UINT64 Rsp; 292 UINT64 Rdx; 293 UINT64 Rcx; 294 UINT64 Rbx; 295 UINT64 Rax; 296 UINT64 Cr8; 297 UINT64 R8; 298 UINT64 R9; 299 UINT64 R10; 300 UINT64 R11; 301 UINT64 R12; 302 UINT64 R13; 303 UINT64 R14; 304 UINT64 R15; 305 } DEBUG_DATA_X64_SYSTEM_CONTEXT; 306 307 #pragma pack() 308 309 #endif 310 311
