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  /external/libxaac/decoder/armv7/
ixheaacd_harm_idx_zerotwolp.s 62 B STORE
74 STORE:
  /external/mesa3d/src/compiler/nir/
nir_intrinsics.h 164 * Image load, store and atomic intrinsics.
173 * in use are undefined. Image store takes an additional four-component
387 * load/store intrinsics. Typically, this is vec4 units for things such as
422 * to store and the second (and possibly third) source specify where to store
427 #define STORE(name, srcs, num_indices, idx0, idx1, idx2, flags) \
431 STORE(output, 2, 3, BASE, WRMASK, COMPONENT, 0)
435 STORE(per_vertex_output, 3, 3, BASE, WRMASK, COMPONENT, 0)
437 STORE(ssbo, 3, 1, WRMASK, xx, xx, 0)
439 STORE(shared, 2, 2, BASE, WRMASK, xx, 0
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  /tools/apkzlib/src/main/java/com/android/tools/build/apkzlib/zip/
CompressionMethod.java 26 * STORE method: data is stored without any compression.
28 STORE(0),
  /external/elfutils/libelf/
gelf_xlate.c 68 #define STORE(Bits, ptr, val) (*(uint##Bits##_t *) ptr = val)
80 #define STORE(Bits, ptr, val) (((union unaligned *) ptr)->u##Bits = val)
99 case 2: STORE (16, dest, bswap_16 (FETCH (16, ptr))); break; \
100 case 4: STORE (32, dest, bswap_32 (FETCH (32, ptr))); break; \
101 case 8: STORE (64, dest, bswap_64 (FETCH (64, ptr))); break; \
  /external/syslinux/gpxe/src/util/Option/
ROM.pm 82 sub STORE {
101 $self->STORE ( $key, 0 );
  /toolchain/binutils/binutils-2.27/gas/testsuite/gas/epiphany/
regression.s 76 /*LOAD-STORE DISPLACEMENT */
84 NEXT: STRB R4,[R0,#0x0] ;//Store Byte
88 STOREB: STRB R5,[R0,#0xf] ;//Store Byte
92 STORES: STRH R4,[R0,#0x0] ;//Store Short
96 STORES2: STRH R5,[R0,#0xe] ;//Store Short
98 VERIFY R63,R63,R5,STORE ;
100 STORE: STR R4,[R0,#0x0] ;//Store Word
104 STORE2: STR R5,[R0,#0xc] ;//Store Word
110 /*LOAD-STORE INDEX *
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  /external/e2fsprogs/lib/ext2fs/
icount.c 35 * one, and then use a sorted list to store the counts for inodes
671 #define STORE 0x02
683 { STORE, 42, 42, 42 },
684 { STORE, 1, 1, 1 },
685 { STORE, 2, 2, 2 },
686 { STORE, 3, 3, 3 },
687 { STORE, 10, 1, 1 },
688 { STORE, 42, 0, 0 },
709 { STORE, 1, 1, 1 },
710 { STORE, 2, 2, 2 }
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  /external/v8/src/compiler/
machine-operator.cc 505 #define STORE(Type) \
506 struct Store##Type##Operator : public Operator1<StoreRepresentation> { \
507 explicit Store##Type##Operator(WriteBarrierKind write_barrier_kind) \
511 "Store", 3, 1, 1, 0, 1, 0, \
515 struct Store##Type##NoWriteBarrier##Operator final \
516 : public Store##Type##Operator { \
517 Store##Type##NoWriteBarrier##Operator() \
518 : Store##Type##Operator(kNoWriteBarrier) {} \
520 struct Store##Type##MapWriteBarrier##Operator final \
521 : public Store##Type##Operator {
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  /packages/apps/Email/provider_src/com/android/email/mail/store/imap/
ImapConstants.java 17 package com.android.email.mail.store.imap;
19 import com.android.email.mail.Store;
29 = String.format(Locale.US, "BODY.PEEK[]<0.%d>", Store.FETCH_BODY_SANE_SUGGESTED_SIZE);
82 public static final String STORE = "STORE";
90 public static final String UID_STORE = "UID STORE";
  /packages/apps/Dialer/java/com/android/voicemail/impl/mail/store/imap/
ImapConstants.java 17 package com.android.voicemail.impl.mail.store.imap;
19 import com.android.voicemail.impl.mail.store.ImapStore;
81 public static final String STORE = "STORE";
89 public static final String UID_STORE = "UID STORE";
  /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
SlotIndexes.h 86 enum Slot { LOAD, USE, DEF, STORE, NUM };
209 /// isStore - Return true if this is a STORE slot.
211 return getSlot() == STORE;
246 /// Returns the index of the STORE slot for the instruction pointed to by
249 return SlotIndex(&entry(), SlotIndex::STORE);
254 /// index is a STORE, the first slot for the next instruction.
260 if (s == SlotIndex::STORE) {
281 return SlotIndex(entry().getPrev(), SlotIndex::STORE);
ISDOpcodes.h 454 // LOAD and STORE have token chains as their first operand, then the same
455 // operands as an LLVM load/store instruction, then an offset node that
458 LOAD, STORE,
592 // OUTCHAIN = MEMBARRIER(INCHAIN, load-load, load-store, store-load,
593 // store-store, device)
610 // This corresponds to "store atomic" instruction.
644 /// MemIndexedMode enum - This enum defines the load / store indexed
647 /// UNINDEXED "Normal" load / store. The effective address is alread
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  /external/webp/src/dsp/
dec.c 29 #define STORE(x, y, v) \
34 STORE(0, y, DC + (d)); \
35 STORE(1, y, DC + (c)); \
36 STORE(2, y, DC - (c)); \
37 STORE(3, y, DC - (d)); \
74 STORE(0, 0, a + d);
75 STORE(1, 0, b + c);
76 STORE(2, 0, b - c);
77 STORE(3, 0, a - d);
118 STORE(i, j, DC)
    [all...]
enc.c 109 #define STORE(x, y, v) \
141 STORE(0, i, a + d);
142 STORE(1, i, b + c);
143 STORE(2, i, b - c);
144 STORE(3, i, a - d);
226 #undef STORE
  /development/samples/ApiDemos/src/com/example/android/mmslib/pdu/
PduHeaders.java 65 public static final int STORE = 0xA2;
130 * X-Mms-Store |
310 * X-Mms-Store-Status field types.
372 case STORE:
  /external/mesa3d/src/gallium/drivers/swr/rasterizer/jitter/
builder_misc.cpp 303 StoreInst *Builder::STORE(Value *val, Value *basePtr, const std::initializer_list<uint32_t> &indices)
308 return STORE(val, GEPA(basePtr, valIndices));
316 return STORE(val, GEPA(basePtr, valIndices));
555 // store vSrc on the stack. this way we can select between a valid load address and the vSrc address
557 STORE(vSrc, vSrcPtr);
605 // store vSrc on the stack. this way we can select between a valid load address and the vSrc address
607 STORE(vSrc, vSrcPtr);
655 // store vSrc on the stack. this way we can select between a valid load address and the vSrc address
657 STORE(vSrc, vSrcPtr);
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  /external/mp4parser/isoparser/src/main/java/com/googlecode/mp4parser/authoring/tracks/
H264TrackImpl.java 223 IGNORE, BUFFER, STORE, END
261 case STORE:
352 action = NALActions.STORE; // Will only work in single slice per frame mode!
  /external/pcre/dist2/src/sljit/
sljitNativeARM_64.c 767 #define STORE 0x01
922 tmp_r = (flags & STORE) ? TMP_REG3 : reg;
    [all...]
sljitNativeARM_T2_32.c 788 #define STORE 0x01
813 s = store
964 FAIL_IF(push_inst16(compiler, STR_SP | ((flags & STORE) ? 0 : 0x800) | RDN3(reg) | (argw >> 2)));
1014 tmp_r = (flags & STORE) ? TMP_REG3 : reg;
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  /external/tensorflow/tensorflow/core/kernels/
sparse_matmul_op.cc 94 // For each block, we store all the non zero entries in data/data3 vector and
101 // vectors respectively. To identify block boundaries, we store the block
272 #define STORE(x, y) Eigen::internal::pstore<float>(x, y);
412 STORE(*out, c1);
413 STORE(*out + kNumOperands, c2);
444 STORE(*out, c1);
445 STORE(*out + kNumOperands, c2);
494 STORE(*out, c1);
495 STORE(*out + kNumOperands, c2);
496 STORE(*out + 2 * kNumOperands, c3)
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  /frameworks/opt/telephony/src/java/com/google/android/mms/pdu/
PduHeaders.java 65 public static final int STORE = 0xA2;
130 * X-Mms-Store |
310 * X-Mms-Store-Status field types.
372 case STORE:
  /packages/apps/Messaging/src/android/support/v7/mms/pdu/
PduHeaders.java 63 public static final int STORE = 0xA2;
128 * X-Mms-Store |
308 * X-Mms-Store-Status field types.
370 case STORE:
  /packages/apps/Messaging/src/com/android/messaging/mmslib/pdu/
PduHeaders.java 66 public static final int STORE = 0xA2;
131 * X-Mms-Store |
328 * X-Mms-Store-Status field types.
390 case STORE:
  /toolchain/binutils/binutils-2.27/bfd/
coff-sh.c 698 a load or store instruction is not aligned on a four byte boundary,
701 align load and store instructions on four byte boundaries if we
996 /* Look for load and store instructions that we can align on four
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  /external/llvm/include/llvm/CodeGen/
ISDOpcodes.h 228 /// indicates if an overflow occurred (*not* a flag, because it may be store
540 /// LOAD and STORE have token chains as their first operand, then the same
541 /// operands as an LLVM load/store instruction, then an offset node that
544 LOAD, STORE,
705 /// This corresponds to "store atomic" instruction.
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