/external/llvm/lib/Target/AMDGPU/ |
SILowerI1Copies.cpp | 103 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); 106 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { 133 SrcRC == &AMDGPU::VReg_1RegClass) {
|
SIFixSGPRCopies.cpp | 135 const TargetRegisterClass *SrcRC = 141 // SrcRC = TRI.getSubRegClass(SrcRC, Copy.getOperand(1).getSubReg()); 148 return std::make_pair(SrcRC, DstRC); 151 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC, 154 return TRI.isSGPRClass(DstRC) && TRI.hasVGPRs(SrcRC); 157 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC, 160 return TRI.isSGPRClass(SrcRC) && TRI.hasVGPRs(DstRC); 193 const TargetRegisterClass *SrcRC, *DstRC; 194 std::tie(SrcRC, DstRC) = getCopyRegClasses(CopyUse, *TRI, MRI) [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXInstrInfo.cpp | 39 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 41 if (DestRC->getSize() != SrcRC->getSize()) 50 Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr 53 Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr 56 Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr 59 Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
|
/external/llvm/lib/Target/PowerPC/ |
PPCVSXCopy.cpp | 106 const TargetRegisterClass *SrcRC = 115 unsigned NewVReg = MRI.createVirtualRegister(SrcRC);
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 157 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; 158 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 172 if (MatchReg && SrcRC->getCopyCost() < 0) { [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
InstrEmitter.cpp | 137 const TargetRegisterClass *SrcRC = 0, *DstRC = 0; 138 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); 152 if (MatchReg && SrcRC->getCopyCost() < 0) { [all...] |
/external/llvm/lib/CodeGen/ |
DetectDeadLanes.cpp | 161 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); 162 if (DstRC == SrcRC) 187 return !TRI.getCommonSuperRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx, PreA, 190 return !TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSubIdx); 192 return !TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSubIdx); 193 return !TRI.getCommonSubClass(SrcRC, DstRC);
|
PeepholeOptimizer.cpp | 684 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg); 685 ShouldRewrite = TRI->shouldRewriteCopySrc(DefRC, SubReg, SrcRC, [all...] |
RegisterCoalescer.cpp | 352 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 361 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, 368 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 372 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); 375 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 390 CrossClass = NewRC != DstRC || NewRC != SrcRC; [all...] |
/external/swiftshader/third_party/LLVM/lib/CodeGen/ |
RegisterCoalescer.cpp | 156 const TargetRegisterClass *SrcRC, 289 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 291 if (!TRI.getCommonSubClass(DstRC, SrcRC)) 306 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); 309 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); 311 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); 314 CrossClass = NewRC != DstRC || NewRC != SrcRC; [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
X86FastISel.cpp | 780 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 782 if (!SrcRC->contains(DstReg)) [all...] |
/external/llvm/lib/Target/ARM/ |
ARMFastISel.cpp | [all...] |
/external/llvm/lib/Target/X86/ |
X86FastISel.cpp | [all...] |