1 /* 2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __XLAT_TABLES_DEFS_H__ 8 #define __XLAT_TABLES_DEFS_H__ 9 10 #include <arch.h> 11 #include <utils_def.h> 12 13 /* Miscellaneous MMU related constants */ 14 #define NUM_2MB_IN_GB (U(1) << 9) 15 #define NUM_4K_IN_2MB (U(1) << 9) 16 #define NUM_GB_IN_4GB (U(1) << 2) 17 18 #define TWO_MB_SHIFT U(21) 19 #define ONE_GB_SHIFT U(30) 20 #define FOUR_KB_SHIFT U(12) 21 22 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 23 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 24 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 25 26 #define INVALID_DESC U(0x0) 27 /* 28 * A block descriptor points to a region of memory bigger than the granule size 29 * (e.g. a 2MB region when the granule size is 4KB). 30 */ 31 #define BLOCK_DESC U(0x1) /* Table levels 0-2 */ 32 /* A table descriptor points to the next level of translation table. */ 33 #define TABLE_DESC U(0x3) /* Table levels 0-2 */ 34 /* 35 * A page descriptor points to a page, i.e. a memory region whose size is the 36 * translation granule size (e.g. 4KB). 37 */ 38 #define PAGE_DESC U(0x3) /* Table level 3 */ 39 40 #define DESC_MASK U(0x3) 41 42 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 43 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 44 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 45 46 /* XN: Translation regimes that support one VA range (EL2 and EL3). */ 47 #define XN (ULL(1) << 2) 48 /* UXN, PXN: Translation regimes that support two VA ranges (EL1&0). */ 49 #define UXN (ULL(1) << 2) 50 #define PXN (ULL(1) << 1) 51 #define CONT_HINT (ULL(1) << 0) 52 #define UPPER_ATTRS(x) (((x) & ULL(0x7)) << 52) 53 54 #define NON_GLOBAL (U(1) << 9) 55 #define ACCESS_FLAG (U(1) << 8) 56 #define NSH (U(0x0) << 6) 57 #define OSH (U(0x2) << 6) 58 #define ISH (U(0x3) << 6) 59 60 #define TABLE_ADDR_MASK ULL(0x0000FFFFFFFFF000) 61 62 /* 63 * The ARMv8-A architecture allows translation granule sizes of 4KB, 16KB or 64 * 64KB. However, TF only supports the 4KB case at the moment. 65 */ 66 #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT 67 #define PAGE_SIZE (U(1) << PAGE_SIZE_SHIFT) 68 #define PAGE_SIZE_MASK (PAGE_SIZE - 1) 69 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) 70 71 #define XLAT_ENTRY_SIZE_SHIFT U(3) /* Each MMU table entry is 8 bytes (1 << 3) */ 72 #define XLAT_ENTRY_SIZE (U(1) << XLAT_ENTRY_SIZE_SHIFT) 73 74 #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT /* Size of one complete table */ 75 #define XLAT_TABLE_SIZE (U(1) << XLAT_TABLE_SIZE_SHIFT) 76 77 #define XLAT_TABLE_LEVEL_MAX U(3) 78 79 /* Values for number of entries in each MMU translation table */ 80 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 81 #define XLAT_TABLE_ENTRIES (U(1) << XLAT_TABLE_ENTRIES_SHIFT) 82 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) 83 84 /* Values to convert a memory address to an index into a translation table */ 85 #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 86 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 87 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 88 #define L0_XLAT_ADDRESS_SHIFT (L1_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 89 #define XLAT_ADDR_SHIFT(level) (PAGE_SIZE_SHIFT + \ 90 ((XLAT_TABLE_LEVEL_MAX - (level)) * XLAT_TABLE_ENTRIES_SHIFT)) 91 92 #define XLAT_BLOCK_SIZE(level) ((u_register_t)1 << XLAT_ADDR_SHIFT(level)) 93 /* Mask to get the bits used to index inside a block of a certain level */ 94 #define XLAT_BLOCK_MASK(level) (XLAT_BLOCK_SIZE(level) - 1) 95 /* Mask to get the address bits common to a block of a certain table level*/ 96 #define XLAT_ADDR_MASK(level) (~XLAT_BLOCK_MASK(level)) 97 /* 98 * Extract from the given virtual address the index into the given lookup level. 99 * This macro assumes the system is using the 4KB translation granule. 100 */ 101 #define XLAT_TABLE_IDX(virtual_addr, level) \ 102 (((virtual_addr) >> XLAT_ADDR_SHIFT(level)) & ULL(0x1FF)) 103 104 /* 105 * The ARMv8 translation table descriptor format defines AP[2:1] as the Access 106 * Permissions bits, and does not define an AP[0] bit. 107 * 108 * AP[1] is valid only for a stage 1 translation that supports two VA ranges 109 * (i.e. in the ARMv8A.0 architecture, that is the S-EL1&0 regime). 110 * 111 * AP[1] is RES0 for stage 1 translations that support only one VA range 112 * (e.g. EL3). 113 */ 114 #define AP2_SHIFT U(0x7) 115 #define AP2_RO U(0x1) 116 #define AP2_RW U(0x0) 117 118 #define AP1_SHIFT U(0x6) 119 #define AP1_ACCESS_UNPRIVILEGED U(0x1) 120 #define AP1_NO_ACCESS_UNPRIVILEGED U(0x0) 121 122 /* 123 * The following definitions must all be passed to the LOWER_ATTRS() macro to 124 * get the right bitmask. 125 */ 126 #define AP_RO (AP2_RO << 5) 127 #define AP_RW (AP2_RW << 5) 128 #define AP_ACCESS_UNPRIVILEGED (AP1_ACCESS_UNPRIVILEGED << 4) 129 #define AP_NO_ACCESS_UNPRIVILEGED (AP1_NO_ACCESS_UNPRIVILEGED << 4) 130 #define NS (U(0x1) << 3) 131 #define ATTR_NON_CACHEABLE_INDEX U(0x2) 132 #define ATTR_DEVICE_INDEX U(0x1) 133 #define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0) 134 #define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2) 135 136 /* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */ 137 #define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC) 138 /* Device-nGnRE */ 139 #define ATTR_DEVICE MAIR_DEV_nGnRE 140 /* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */ 141 #define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA) 142 #define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3)) 143 #define ATTR_INDEX_MASK U(0x3) 144 #define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK) 145 146 /* 147 * Shift values for the attributes fields in a block or page descriptor. 148 * See section D4.3.3 in the ARMv8-A ARM (issue B.a). 149 */ 150 151 /* Memory attributes index field, AttrIndx[2:0]. */ 152 #define ATTR_INDEX_SHIFT 2 153 /* Non-secure bit, NS. */ 154 #define NS_SHIFT 5 155 /* Shareability field, SH[1:0] */ 156 #define SHAREABILITY_SHIFT 8 157 /* The Access Flag, AF. */ 158 #define ACCESS_FLAG_SHIFT 10 159 /* The not global bit, nG. */ 160 #define NOT_GLOBAL_SHIFT 11 161 /* Contiguous hint bit. */ 162 #define CONT_HINT_SHIFT 52 163 /* Execute-never bits, XN. */ 164 #define PXN_SHIFT 53 165 #define XN_SHIFT 54 166 #define UXN_SHIFT XN_SHIFT 167 168 /* 169 * Flags to override default values used to program system registers while 170 * enabling the MMU. 171 */ 172 #define DISABLE_DCACHE (U(1) << 0) 173 174 /* 175 * This flag marks the translation tables are Non-cacheable for MMU accesses. 176 * If the flag is not specified, by default the tables are cacheable. 177 */ 178 #define XLAT_TABLE_NC (U(1) << 1) 179 180 #endif /* __XLAT_TABLES_DEFS_H__ */ 181
