1 //===---------------------------- libunwind.h -----------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is dual licensed under the MIT and the University of Illinois Open 6 // Source Licenses. See LICENSE.TXT for details. 7 // 8 // 9 // Compatible with libunwind API documented at: 10 // http://www.nongnu.org/libunwind/man/libunwind(3).html 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef __LIBUNWIND__ 15 #define __LIBUNWIND__ 16 17 #include <__libunwind_config.h> 18 19 #include <stdint.h> 20 #include <stddef.h> 21 22 #ifdef __APPLE__ 23 #if __clang__ 24 #if __has_include(<Availability.h>) 25 #include <Availability.h> 26 #endif 27 #elif __ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__ >= 1050 28 #include <Availability.h> 29 #endif 30 31 #ifdef __arm__ 32 #define LIBUNWIND_AVAIL __attribute__((unavailable)) 33 #elif defined(__OSX_AVAILABLE_STARTING) 34 #define LIBUNWIND_AVAIL __OSX_AVAILABLE_STARTING(__MAC_10_6, __IPHONE_5_0) 35 #else 36 #include <AvailabilityMacros.h> 37 #ifdef AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 38 #define LIBUNWIND_AVAIL AVAILABLE_MAC_OS_X_VERSION_10_6_AND_LATER 39 #else 40 #define LIBUNWIND_AVAIL __attribute__((unavailable)) 41 #endif 42 #endif 43 #else 44 #define LIBUNWIND_AVAIL 45 #endif 46 47 /* error codes */ 48 enum { 49 UNW_ESUCCESS = 0, /* no error */ 50 UNW_EUNSPEC = -6540, /* unspecified (general) error */ 51 UNW_ENOMEM = -6541, /* out of memory */ 52 UNW_EBADREG = -6542, /* bad register number */ 53 UNW_EREADONLYREG = -6543, /* attempt to write read-only register */ 54 UNW_ESTOPUNWIND = -6544, /* stop unwinding */ 55 UNW_EINVALIDIP = -6545, /* invalid IP */ 56 UNW_EBADFRAME = -6546, /* bad frame */ 57 UNW_EINVAL = -6547, /* unsupported operation or bad value */ 58 UNW_EBADVERSION = -6548, /* unwind info has unsupported version */ 59 UNW_ENOINFO = -6549 /* no unwind info found */ 60 }; 61 62 struct unw_context_t { 63 uint64_t data[_LIBUNWIND_CONTEXT_SIZE]; 64 }; 65 typedef struct unw_context_t unw_context_t; 66 67 struct unw_cursor_t { 68 uint64_t data[_LIBUNWIND_CURSOR_SIZE]; 69 }; 70 typedef struct unw_cursor_t unw_cursor_t; 71 72 typedef struct unw_addr_space *unw_addr_space_t; 73 74 typedef int unw_regnum_t; 75 typedef uintptr_t unw_word_t; 76 #if defined(__arm__) 77 typedef uint64_t unw_fpreg_t; 78 #else 79 typedef double unw_fpreg_t; 80 #endif 81 82 struct unw_proc_info_t { 83 unw_word_t start_ip; /* start address of function */ 84 unw_word_t end_ip; /* address after end of function */ 85 unw_word_t lsda; /* address of language specific data area, */ 86 /* or zero if not used */ 87 unw_word_t handler; /* personality routine, or zero if not used */ 88 unw_word_t gp; /* not used */ 89 unw_word_t flags; /* not used */ 90 uint32_t format; /* compact unwind encoding, or zero if none */ 91 uint32_t unwind_info_size; /* size of DWARF unwind info, or zero if none */ 92 unw_word_t unwind_info; /* address of DWARF unwind info, or zero */ 93 unw_word_t extra; /* mach_header of mach-o image containing func */ 94 }; 95 typedef struct unw_proc_info_t unw_proc_info_t; 96 97 #ifdef __cplusplus 98 extern "C" { 99 #endif 100 101 extern int unw_getcontext(unw_context_t *) LIBUNWIND_AVAIL; 102 extern int unw_init_local(unw_cursor_t *, unw_context_t *) LIBUNWIND_AVAIL; 103 extern int unw_step(unw_cursor_t *) LIBUNWIND_AVAIL; 104 extern int unw_get_reg(unw_cursor_t *, unw_regnum_t, unw_word_t *) LIBUNWIND_AVAIL; 105 extern int unw_get_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t *) LIBUNWIND_AVAIL; 106 extern int unw_set_reg(unw_cursor_t *, unw_regnum_t, unw_word_t) LIBUNWIND_AVAIL; 107 extern int unw_set_fpreg(unw_cursor_t *, unw_regnum_t, unw_fpreg_t) LIBUNWIND_AVAIL; 108 extern int unw_resume(unw_cursor_t *) LIBUNWIND_AVAIL; 109 110 #ifdef __arm__ 111 /* Save VFP registers in FSTMX format (instead of FSTMD). */ 112 extern void unw_save_vfp_as_X(unw_cursor_t *) LIBUNWIND_AVAIL; 113 #endif 114 115 116 extern const char *unw_regname(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 117 extern int unw_get_proc_info(unw_cursor_t *, unw_proc_info_t *) LIBUNWIND_AVAIL; 118 extern int unw_is_fpreg(unw_cursor_t *, unw_regnum_t) LIBUNWIND_AVAIL; 119 extern int unw_is_signal_frame(unw_cursor_t *) LIBUNWIND_AVAIL; 120 extern int unw_get_proc_name(unw_cursor_t *, char *, size_t, unw_word_t *) LIBUNWIND_AVAIL; 121 //extern int unw_get_save_loc(unw_cursor_t*, int, unw_save_loc_t*); 122 123 extern unw_addr_space_t unw_local_addr_space; 124 125 #ifdef UNW_REMOTE 126 /* 127 * Mac OS X "remote" API for unwinding other processes on same machine 128 * 129 */ 130 extern unw_addr_space_t unw_create_addr_space_for_task(task_t); 131 extern void unw_destroy_addr_space(unw_addr_space_t); 132 extern int unw_init_remote_thread(unw_cursor_t *, unw_addr_space_t, thread_t *); 133 #endif /* UNW_REMOTE */ 134 135 /* 136 * traditional libunwind "remote" API 137 * NOT IMPLEMENTED on Mac OS X 138 * 139 * extern int unw_init_remote(unw_cursor_t*, unw_addr_space_t, 140 * thread_t*); 141 * extern unw_accessors_t unw_get_accessors(unw_addr_space_t); 142 * extern unw_addr_space_t unw_create_addr_space(unw_accessors_t, int); 143 * extern void unw_flush_cache(unw_addr_space_t, unw_word_t, 144 * unw_word_t); 145 * extern int unw_set_caching_policy(unw_addr_space_t, 146 * unw_caching_policy_t); 147 * extern void _U_dyn_register(unw_dyn_info_t*); 148 * extern void _U_dyn_cancel(unw_dyn_info_t*); 149 */ 150 151 #ifdef __cplusplus 152 } 153 #endif 154 155 // architecture independent register numbers 156 enum { 157 UNW_REG_IP = -1, // instruction pointer 158 UNW_REG_SP = -2, // stack pointer 159 }; 160 161 // 32-bit x86 registers 162 enum { 163 UNW_X86_EAX = 0, 164 UNW_X86_ECX = 1, 165 UNW_X86_EDX = 2, 166 UNW_X86_EBX = 3, 167 UNW_X86_EBP = 4, 168 UNW_X86_ESP = 5, 169 UNW_X86_ESI = 6, 170 UNW_X86_EDI = 7 171 }; 172 173 // 64-bit x86_64 registers 174 enum { 175 UNW_X86_64_RAX = 0, 176 UNW_X86_64_RDX = 1, 177 UNW_X86_64_RCX = 2, 178 UNW_X86_64_RBX = 3, 179 UNW_X86_64_RSI = 4, 180 UNW_X86_64_RDI = 5, 181 UNW_X86_64_RBP = 6, 182 UNW_X86_64_RSP = 7, 183 UNW_X86_64_R8 = 8, 184 UNW_X86_64_R9 = 9, 185 UNW_X86_64_R10 = 10, 186 UNW_X86_64_R11 = 11, 187 UNW_X86_64_R12 = 12, 188 UNW_X86_64_R13 = 13, 189 UNW_X86_64_R14 = 14, 190 UNW_X86_64_R15 = 15, 191 UNW_X86_64_RIP = 16, 192 UNW_X86_64_XMM0 = 17, 193 UNW_X86_64_XMM1 = 18, 194 UNW_X86_64_XMM2 = 19, 195 UNW_X86_64_XMM3 = 20, 196 UNW_X86_64_XMM4 = 21, 197 UNW_X86_64_XMM5 = 22, 198 UNW_X86_64_XMM6 = 23, 199 UNW_X86_64_XMM7 = 24, 200 UNW_X86_64_XMM8 = 25, 201 UNW_X86_64_XMM9 = 26, 202 UNW_X86_64_XMM10 = 27, 203 UNW_X86_64_XMM11 = 28, 204 UNW_X86_64_XMM12 = 29, 205 UNW_X86_64_XMM13 = 30, 206 UNW_X86_64_XMM14 = 31, 207 UNW_X86_64_XMM15 = 32, 208 }; 209 210 211 // 32-bit ppc register numbers 212 enum { 213 UNW_PPC_R0 = 0, 214 UNW_PPC_R1 = 1, 215 UNW_PPC_R2 = 2, 216 UNW_PPC_R3 = 3, 217 UNW_PPC_R4 = 4, 218 UNW_PPC_R5 = 5, 219 UNW_PPC_R6 = 6, 220 UNW_PPC_R7 = 7, 221 UNW_PPC_R8 = 8, 222 UNW_PPC_R9 = 9, 223 UNW_PPC_R10 = 10, 224 UNW_PPC_R11 = 11, 225 UNW_PPC_R12 = 12, 226 UNW_PPC_R13 = 13, 227 UNW_PPC_R14 = 14, 228 UNW_PPC_R15 = 15, 229 UNW_PPC_R16 = 16, 230 UNW_PPC_R17 = 17, 231 UNW_PPC_R18 = 18, 232 UNW_PPC_R19 = 19, 233 UNW_PPC_R20 = 20, 234 UNW_PPC_R21 = 21, 235 UNW_PPC_R22 = 22, 236 UNW_PPC_R23 = 23, 237 UNW_PPC_R24 = 24, 238 UNW_PPC_R25 = 25, 239 UNW_PPC_R26 = 26, 240 UNW_PPC_R27 = 27, 241 UNW_PPC_R28 = 28, 242 UNW_PPC_R29 = 29, 243 UNW_PPC_R30 = 30, 244 UNW_PPC_R31 = 31, 245 UNW_PPC_F0 = 32, 246 UNW_PPC_F1 = 33, 247 UNW_PPC_F2 = 34, 248 UNW_PPC_F3 = 35, 249 UNW_PPC_F4 = 36, 250 UNW_PPC_F5 = 37, 251 UNW_PPC_F6 = 38, 252 UNW_PPC_F7 = 39, 253 UNW_PPC_F8 = 40, 254 UNW_PPC_F9 = 41, 255 UNW_PPC_F10 = 42, 256 UNW_PPC_F11 = 43, 257 UNW_PPC_F12 = 44, 258 UNW_PPC_F13 = 45, 259 UNW_PPC_F14 = 46, 260 UNW_PPC_F15 = 47, 261 UNW_PPC_F16 = 48, 262 UNW_PPC_F17 = 49, 263 UNW_PPC_F18 = 50, 264 UNW_PPC_F19 = 51, 265 UNW_PPC_F20 = 52, 266 UNW_PPC_F21 = 53, 267 UNW_PPC_F22 = 54, 268 UNW_PPC_F23 = 55, 269 UNW_PPC_F24 = 56, 270 UNW_PPC_F25 = 57, 271 UNW_PPC_F26 = 58, 272 UNW_PPC_F27 = 59, 273 UNW_PPC_F28 = 60, 274 UNW_PPC_F29 = 61, 275 UNW_PPC_F30 = 62, 276 UNW_PPC_F31 = 63, 277 UNW_PPC_MQ = 64, 278 UNW_PPC_LR = 65, 279 UNW_PPC_CTR = 66, 280 UNW_PPC_AP = 67, 281 UNW_PPC_CR0 = 68, 282 UNW_PPC_CR1 = 69, 283 UNW_PPC_CR2 = 70, 284 UNW_PPC_CR3 = 71, 285 UNW_PPC_CR4 = 72, 286 UNW_PPC_CR5 = 73, 287 UNW_PPC_CR6 = 74, 288 UNW_PPC_CR7 = 75, 289 UNW_PPC_XER = 76, 290 UNW_PPC_V0 = 77, 291 UNW_PPC_V1 = 78, 292 UNW_PPC_V2 = 79, 293 UNW_PPC_V3 = 80, 294 UNW_PPC_V4 = 81, 295 UNW_PPC_V5 = 82, 296 UNW_PPC_V6 = 83, 297 UNW_PPC_V7 = 84, 298 UNW_PPC_V8 = 85, 299 UNW_PPC_V9 = 86, 300 UNW_PPC_V10 = 87, 301 UNW_PPC_V11 = 88, 302 UNW_PPC_V12 = 89, 303 UNW_PPC_V13 = 90, 304 UNW_PPC_V14 = 91, 305 UNW_PPC_V15 = 92, 306 UNW_PPC_V16 = 93, 307 UNW_PPC_V17 = 94, 308 UNW_PPC_V18 = 95, 309 UNW_PPC_V19 = 96, 310 UNW_PPC_V20 = 97, 311 UNW_PPC_V21 = 98, 312 UNW_PPC_V22 = 99, 313 UNW_PPC_V23 = 100, 314 UNW_PPC_V24 = 101, 315 UNW_PPC_V25 = 102, 316 UNW_PPC_V26 = 103, 317 UNW_PPC_V27 = 104, 318 UNW_PPC_V28 = 105, 319 UNW_PPC_V29 = 106, 320 UNW_PPC_V30 = 107, 321 UNW_PPC_V31 = 108, 322 UNW_PPC_VRSAVE = 109, 323 UNW_PPC_VSCR = 110, 324 UNW_PPC_SPE_ACC = 111, 325 UNW_PPC_SPEFSCR = 112 326 }; 327 328 // 64-bit ARM64 registers 329 enum { 330 UNW_ARM64_X0 = 0, 331 UNW_ARM64_X1 = 1, 332 UNW_ARM64_X2 = 2, 333 UNW_ARM64_X3 = 3, 334 UNW_ARM64_X4 = 4, 335 UNW_ARM64_X5 = 5, 336 UNW_ARM64_X6 = 6, 337 UNW_ARM64_X7 = 7, 338 UNW_ARM64_X8 = 8, 339 UNW_ARM64_X9 = 9, 340 UNW_ARM64_X10 = 10, 341 UNW_ARM64_X11 = 11, 342 UNW_ARM64_X12 = 12, 343 UNW_ARM64_X13 = 13, 344 UNW_ARM64_X14 = 14, 345 UNW_ARM64_X15 = 15, 346 UNW_ARM64_X16 = 16, 347 UNW_ARM64_X17 = 17, 348 UNW_ARM64_X18 = 18, 349 UNW_ARM64_X19 = 19, 350 UNW_ARM64_X20 = 20, 351 UNW_ARM64_X21 = 21, 352 UNW_ARM64_X22 = 22, 353 UNW_ARM64_X23 = 23, 354 UNW_ARM64_X24 = 24, 355 UNW_ARM64_X25 = 25, 356 UNW_ARM64_X26 = 26, 357 UNW_ARM64_X27 = 27, 358 UNW_ARM64_X28 = 28, 359 UNW_ARM64_X29 = 29, 360 UNW_ARM64_FP = 29, 361 UNW_ARM64_X30 = 30, 362 UNW_ARM64_LR = 30, 363 UNW_ARM64_X31 = 31, 364 UNW_ARM64_SP = 31, 365 // reserved block 366 UNW_ARM64_D0 = 64, 367 UNW_ARM64_D1 = 65, 368 UNW_ARM64_D2 = 66, 369 UNW_ARM64_D3 = 67, 370 UNW_ARM64_D4 = 68, 371 UNW_ARM64_D5 = 69, 372 UNW_ARM64_D6 = 70, 373 UNW_ARM64_D7 = 71, 374 UNW_ARM64_D8 = 72, 375 UNW_ARM64_D9 = 73, 376 UNW_ARM64_D10 = 74, 377 UNW_ARM64_D11 = 75, 378 UNW_ARM64_D12 = 76, 379 UNW_ARM64_D13 = 77, 380 UNW_ARM64_D14 = 78, 381 UNW_ARM64_D15 = 79, 382 UNW_ARM64_D16 = 80, 383 UNW_ARM64_D17 = 81, 384 UNW_ARM64_D18 = 82, 385 UNW_ARM64_D19 = 83, 386 UNW_ARM64_D20 = 84, 387 UNW_ARM64_D21 = 85, 388 UNW_ARM64_D22 = 86, 389 UNW_ARM64_D23 = 87, 390 UNW_ARM64_D24 = 88, 391 UNW_ARM64_D25 = 89, 392 UNW_ARM64_D26 = 90, 393 UNW_ARM64_D27 = 91, 394 UNW_ARM64_D28 = 92, 395 UNW_ARM64_D29 = 93, 396 UNW_ARM64_D30 = 94, 397 UNW_ARM64_D31 = 95, 398 }; 399 400 // 32-bit ARM registers. Numbers match DWARF for ARM spec #3.1 Table 1. 401 // Naming scheme uses recommendations given in Note 4 for VFP-v2 and VFP-v3. 402 // In this scheme, even though the 64-bit floating point registers D0-D31 403 // overlap physically with the 32-bit floating pointer registers S0-S31, 404 // they are given a non-overlapping range of register numbers. 405 // 406 // Commented out ranges are not preserved during unwinding. 407 enum { 408 UNW_ARM_R0 = 0, 409 UNW_ARM_R1 = 1, 410 UNW_ARM_R2 = 2, 411 UNW_ARM_R3 = 3, 412 UNW_ARM_R4 = 4, 413 UNW_ARM_R5 = 5, 414 UNW_ARM_R6 = 6, 415 UNW_ARM_R7 = 7, 416 UNW_ARM_R8 = 8, 417 UNW_ARM_R9 = 9, 418 UNW_ARM_R10 = 10, 419 UNW_ARM_R11 = 11, 420 UNW_ARM_R12 = 12, 421 UNW_ARM_SP = 13, // Logical alias for UNW_REG_SP 422 UNW_ARM_R13 = 13, 423 UNW_ARM_LR = 14, 424 UNW_ARM_R14 = 14, 425 UNW_ARM_IP = 15, // Logical alias for UNW_REG_IP 426 UNW_ARM_R15 = 15, 427 // 16-63 -- OBSOLETE. Used in VFP1 to represent both S0-S31 and D0-D31. 428 UNW_ARM_S0 = 64, 429 UNW_ARM_S1 = 65, 430 UNW_ARM_S2 = 66, 431 UNW_ARM_S3 = 67, 432 UNW_ARM_S4 = 68, 433 UNW_ARM_S5 = 69, 434 UNW_ARM_S6 = 70, 435 UNW_ARM_S7 = 71, 436 UNW_ARM_S8 = 72, 437 UNW_ARM_S9 = 73, 438 UNW_ARM_S10 = 74, 439 UNW_ARM_S11 = 75, 440 UNW_ARM_S12 = 76, 441 UNW_ARM_S13 = 77, 442 UNW_ARM_S14 = 78, 443 UNW_ARM_S15 = 79, 444 UNW_ARM_S16 = 80, 445 UNW_ARM_S17 = 81, 446 UNW_ARM_S18 = 82, 447 UNW_ARM_S19 = 83, 448 UNW_ARM_S20 = 84, 449 UNW_ARM_S21 = 85, 450 UNW_ARM_S22 = 86, 451 UNW_ARM_S23 = 87, 452 UNW_ARM_S24 = 88, 453 UNW_ARM_S25 = 89, 454 UNW_ARM_S26 = 90, 455 UNW_ARM_S27 = 91, 456 UNW_ARM_S28 = 92, 457 UNW_ARM_S29 = 93, 458 UNW_ARM_S30 = 94, 459 UNW_ARM_S31 = 95, 460 // 96-103 -- OBSOLETE. F0-F7. Used by the FPA system. Superseded by VFP. 461 // 104-111 -- wCGR0-wCGR7, ACC0-ACC7 (Intel wireless MMX) 462 UNW_ARM_WR0 = 112, 463 UNW_ARM_WR1 = 113, 464 UNW_ARM_WR2 = 114, 465 UNW_ARM_WR3 = 115, 466 UNW_ARM_WR4 = 116, 467 UNW_ARM_WR5 = 117, 468 UNW_ARM_WR6 = 118, 469 UNW_ARM_WR7 = 119, 470 UNW_ARM_WR8 = 120, 471 UNW_ARM_WR9 = 121, 472 UNW_ARM_WR10 = 122, 473 UNW_ARM_WR11 = 123, 474 UNW_ARM_WR12 = 124, 475 UNW_ARM_WR13 = 125, 476 UNW_ARM_WR14 = 126, 477 UNW_ARM_WR15 = 127, 478 // 128-133 -- SPSR, SPSR_{FIQ|IRQ|ABT|UND|SVC} 479 // 134-143 -- Reserved 480 // 144-150 -- R8_USR-R14_USR 481 // 151-157 -- R8_FIQ-R14_FIQ 482 // 158-159 -- R13_IRQ-R14_IRQ 483 // 160-161 -- R13_ABT-R14_ABT 484 // 162-163 -- R13_UND-R14_UND 485 // 164-165 -- R13_SVC-R14_SVC 486 // 166-191 -- Reserved 487 UNW_ARM_WC0 = 192, 488 UNW_ARM_WC1 = 193, 489 UNW_ARM_WC2 = 194, 490 UNW_ARM_WC3 = 195, 491 // 196-199 -- wC4-wC7 (Intel wireless MMX control) 492 // 200-255 -- Reserved 493 UNW_ARM_D0 = 256, 494 UNW_ARM_D1 = 257, 495 UNW_ARM_D2 = 258, 496 UNW_ARM_D3 = 259, 497 UNW_ARM_D4 = 260, 498 UNW_ARM_D5 = 261, 499 UNW_ARM_D6 = 262, 500 UNW_ARM_D7 = 263, 501 UNW_ARM_D8 = 264, 502 UNW_ARM_D9 = 265, 503 UNW_ARM_D10 = 266, 504 UNW_ARM_D11 = 267, 505 UNW_ARM_D12 = 268, 506 UNW_ARM_D13 = 269, 507 UNW_ARM_D14 = 270, 508 UNW_ARM_D15 = 271, 509 UNW_ARM_D16 = 272, 510 UNW_ARM_D17 = 273, 511 UNW_ARM_D18 = 274, 512 UNW_ARM_D19 = 275, 513 UNW_ARM_D20 = 276, 514 UNW_ARM_D21 = 277, 515 UNW_ARM_D22 = 278, 516 UNW_ARM_D23 = 279, 517 UNW_ARM_D24 = 280, 518 UNW_ARM_D25 = 281, 519 UNW_ARM_D26 = 282, 520 UNW_ARM_D27 = 283, 521 UNW_ARM_D28 = 284, 522 UNW_ARM_D29 = 285, 523 UNW_ARM_D30 = 286, 524 UNW_ARM_D31 = 287, 525 // 288-319 -- Reserved for VFP/Neon 526 // 320-8191 -- Reserved 527 // 8192-16383 -- Unspecified vendor co-processor register. 528 }; 529 530 // OpenRISC1000 register numbers 531 enum { 532 UNW_OR1K_R0 = 0, 533 UNW_OR1K_R1 = 1, 534 UNW_OR1K_R2 = 2, 535 UNW_OR1K_R3 = 3, 536 UNW_OR1K_R4 = 4, 537 UNW_OR1K_R5 = 5, 538 UNW_OR1K_R6 = 6, 539 UNW_OR1K_R7 = 7, 540 UNW_OR1K_R8 = 8, 541 UNW_OR1K_R9 = 9, 542 UNW_OR1K_R10 = 10, 543 UNW_OR1K_R11 = 11, 544 UNW_OR1K_R12 = 12, 545 UNW_OR1K_R13 = 13, 546 UNW_OR1K_R14 = 14, 547 UNW_OR1K_R15 = 15, 548 UNW_OR1K_R16 = 16, 549 UNW_OR1K_R17 = 17, 550 UNW_OR1K_R18 = 18, 551 UNW_OR1K_R19 = 19, 552 UNW_OR1K_R20 = 20, 553 UNW_OR1K_R21 = 21, 554 UNW_OR1K_R22 = 22, 555 UNW_OR1K_R23 = 23, 556 UNW_OR1K_R24 = 24, 557 UNW_OR1K_R25 = 25, 558 UNW_OR1K_R26 = 26, 559 UNW_OR1K_R27 = 27, 560 UNW_OR1K_R28 = 28, 561 UNW_OR1K_R29 = 29, 562 UNW_OR1K_R30 = 30, 563 UNW_OR1K_R31 = 31, 564 }; 565 566 // MIPS registers 567 enum { 568 UNW_MIPS_R0 = 0, 569 UNW_MIPS_R1 = 1, 570 UNW_MIPS_R2 = 2, 571 UNW_MIPS_R3 = 3, 572 UNW_MIPS_R4 = 4, 573 UNW_MIPS_R5 = 5, 574 UNW_MIPS_R6 = 6, 575 UNW_MIPS_R7 = 7, 576 UNW_MIPS_R8 = 8, 577 UNW_MIPS_R9 = 9, 578 UNW_MIPS_R10 = 10, 579 UNW_MIPS_R11 = 11, 580 UNW_MIPS_R12 = 12, 581 UNW_MIPS_R13 = 13, 582 UNW_MIPS_R14 = 14, 583 UNW_MIPS_R15 = 15, 584 UNW_MIPS_R16 = 16, 585 UNW_MIPS_R17 = 17, 586 UNW_MIPS_R18 = 18, 587 UNW_MIPS_R19 = 19, 588 UNW_MIPS_R20 = 20, 589 UNW_MIPS_R21 = 21, 590 UNW_MIPS_R22 = 22, 591 UNW_MIPS_R23 = 23, 592 UNW_MIPS_R24 = 24, 593 UNW_MIPS_R25 = 25, 594 UNW_MIPS_R26 = 26, 595 UNW_MIPS_R27 = 27, 596 UNW_MIPS_R28 = 28, 597 UNW_MIPS_R29 = 29, 598 UNW_MIPS_R30 = 30, 599 UNW_MIPS_R31 = 31, 600 UNW_MIPS_HI = 64, 601 UNW_MIPS_LO = 65, 602 }; 603 604 #endif 605
