1 /** @file 2 3 The definition for UHCI register operation routines. 4 5 Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR> 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #ifndef _EFI_UHCI_REG_H_ 17 #define _EFI_UHCI_REG_H_ 18 19 // 20 // UHCI register offset 21 // 22 23 #define UHCI_FRAME_NUM 1024 24 25 // 26 // Register offset and PCI related staff 27 // 28 #define USB_BAR_INDEX 4 29 30 #define USBCMD_OFFSET 0 31 #define USBSTS_OFFSET 2 32 #define USBINTR_OFFSET 4 33 #define USBPORTSC_OFFSET 0x10 34 #define USB_FRAME_NO_OFFSET 6 35 #define USB_FRAME_BASE_OFFSET 8 36 #define USB_EMULATION_OFFSET 0xC0 37 38 // 39 // Packet IDs 40 // 41 #define SETUP_PACKET_ID 0x2D 42 #define INPUT_PACKET_ID 0x69 43 #define OUTPUT_PACKET_ID 0xE1 44 #define ERROR_PACKET_ID 0x55 45 46 // 47 // USB port status and control bit definition. 48 // 49 #define USBPORTSC_CCS BIT0 // Current Connect Status 50 #define USBPORTSC_CSC BIT1 // Connect Status Change 51 #define USBPORTSC_PED BIT2 // Port Enable / Disable 52 #define USBPORTSC_PEDC BIT3 // Port Enable / Disable Change 53 #define USBPORTSC_LSL BIT4 // Line Status Low BIT 54 #define USBPORTSC_LSH BIT5 // Line Status High BIT 55 #define USBPORTSC_RD BIT6 // Resume Detect 56 #define USBPORTSC_LSDA BIT8 // Low Speed Device Attached 57 #define USBPORTSC_PR BIT9 // Port Reset 58 #define USBPORTSC_SUSP BIT12 // Suspend 59 60 // 61 // UHCI Spec said it must implement 2 ports each host at least, 62 // and if more, check whether the bit7 of PORTSC is always 1. 63 // So here assume the max of port number each host is 16. 64 // 65 #define USB_MAX_ROOTHUB_PORT 0x0F 66 67 // 68 // Command register bit definitions 69 // 70 #define USBCMD_RS BIT0 // Run/Stop 71 #define USBCMD_HCRESET BIT1 // Host reset 72 #define USBCMD_GRESET BIT2 // Global reset 73 #define USBCMD_EGSM BIT3 // Global Suspend Mode 74 #define USBCMD_FGR BIT4 // Force Global Resume 75 #define USBCMD_SWDBG BIT5 // SW Debug mode 76 #define USBCMD_CF BIT6 // Config Flag (sw only) 77 #define USBCMD_MAXP BIT7 // Max Packet (0 = 32, 1 = 64) 78 79 // 80 // USB Status register bit definitions 81 // 82 #define USBSTS_USBINT BIT0 // Interrupt due to IOC 83 #define USBSTS_ERROR BIT1 // Interrupt due to error 84 #define USBSTS_RD BIT2 // Resume Detect 85 #define USBSTS_HSE BIT3 // Host System Error 86 #define USBSTS_HCPE BIT4 // Host Controller Process Error 87 #define USBSTS_HCH BIT5 // HC Halted 88 89 #define USBTD_ACTIVE BIT7 // TD is still active 90 #define USBTD_STALLED BIT6 // TD is stalled 91 #define USBTD_BUFFERR BIT5 // Buffer underflow or overflow 92 #define USBTD_BABBLE BIT4 // Babble condition 93 #define USBTD_NAK BIT3 // NAK is received 94 #define USBTD_CRC BIT2 // CRC/Time out error 95 #define USBTD_BITSTUFF BIT1 // Bit stuff error 96 97 98 /** 99 Read a UHCI register. 100 101 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 102 @param Offset Register offset to USB_BAR_INDEX. 103 104 @return Content of register. 105 106 **/ 107 UINT16 108 UhciReadReg ( 109 IN EFI_PCI_IO_PROTOCOL *PciIo, 110 IN UINT32 Offset 111 ); 112 113 114 115 /** 116 Write data to UHCI register. 117 118 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 119 @param Offset Register offset to USB_BAR_INDEX. 120 @param Data Data to write. 121 122 @return None. 123 124 **/ 125 VOID 126 UhciWriteReg ( 127 IN EFI_PCI_IO_PROTOCOL *PciIo, 128 IN UINT32 Offset, 129 IN UINT16 Data 130 ); 131 132 133 134 /** 135 Set a bit of the UHCI Register. 136 137 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 138 @param Offset Register offset to USB_BAR_INDEX. 139 @param Bit The bit to set. 140 141 @return None. 142 143 **/ 144 VOID 145 UhciSetRegBit ( 146 IN EFI_PCI_IO_PROTOCOL *PciIo, 147 IN UINT32 Offset, 148 IN UINT16 Bit 149 ); 150 151 152 153 /** 154 Clear a bit of the UHCI Register. 155 156 @param PciIo The PCI_IO protocol to access the PCI. 157 @param Offset Register offset to USB_BAR_INDEX. 158 @param Bit The bit to clear. 159 160 @return None. 161 162 **/ 163 VOID 164 UhciClearRegBit ( 165 IN EFI_PCI_IO_PROTOCOL *PciIo, 166 IN UINT32 Offset, 167 IN UINT16 Bit 168 ); 169 170 171 /** 172 Clear all the interrutp status bits, these bits 173 are Write-Clean. 174 175 @param Uhc The UHCI device. 176 177 @return None. 178 179 **/ 180 VOID 181 UhciAckAllInterrupt ( 182 IN USB_HC_DEV *Uhc 183 ); 184 185 186 /** 187 Stop the host controller. 188 189 @param Uhc The UHCI device. 190 @param Timeout Max time allowed. 191 192 @retval EFI_SUCCESS The host controller is stopped. 193 @retval EFI_TIMEOUT Failed to stop the host controller. 194 195 **/ 196 EFI_STATUS 197 UhciStopHc ( 198 IN USB_HC_DEV *Uhc, 199 IN UINTN Timeout 200 ); 201 202 203 204 /** 205 Check whether the host controller operates well. 206 207 @param PciIo The PCI_IO protocol to use. 208 209 @retval TRUE Host controller is working. 210 @retval FALSE Host controller is halted or system error. 211 212 **/ 213 BOOLEAN 214 UhciIsHcWorking ( 215 IN EFI_PCI_IO_PROTOCOL *PciIo 216 ); 217 218 219 /** 220 Set the UHCI frame list base address. It can't use 221 UhciWriteReg which access memory in UINT16. 222 223 @param PciIo The EFI_PCI_IO_PROTOCOL to use. 224 @param Addr Address to set. 225 226 @return None. 227 228 **/ 229 VOID 230 UhciSetFrameListBaseAddr ( 231 IN EFI_PCI_IO_PROTOCOL *PciIo, 232 IN VOID *Addr 233 ); 234 235 236 /** 237 Disable USB Emulation. 238 239 @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use. 240 241 @return None. 242 243 **/ 244 VOID 245 UhciTurnOffUsbEmulation ( 246 IN EFI_PCI_IO_PROTOCOL *PciIo 247 ); 248 #endif 249
