1 #ifndef STATE_3D_XML 2 #define STATE_3D_XML 3 4 /* Autogenerated file, DO NOT EDIT manually! 5 6 This file was generated by the rules-ng-ng headergen tool in this git repository: 7 http://0x04.net/cgit/index.cgi/rules-ng-ng 8 git clone git://0x04.net/rules-ng-ng 9 10 The rules-ng-ng source files this header was generated from are: 11 - state.xml ( 19792 bytes, from 2016-11-16 18:54:37) 12 - common.xml ( 23422 bytes, from 2016-11-16 18:54:37) 13 - state_hi.xml ( 25653 bytes, from 2016-10-02 14:26:13) 14 - copyright.xml ( 1597 bytes, from 2016-10-02 14:26:13) 15 - state_2d.xml ( 51552 bytes, from 2016-10-02 14:26:13) 16 - state_3d.xml ( 57579 bytes, from 2016-11-16 18:54:37) 17 - state_vg.xml ( 5975 bytes, from 2016-10-02 14:26:13) 18 19 Copyright (C) 2012-2016 by the following authors: 20 - Wladimir J. van der Laan <laanwj (at) gmail.com> 21 - Christian Gmeiner <christian.gmeiner (at) gmail.com> 22 - Lucas Stach <l.stach (at) pengutronix.de> 23 - Russell King <rmk (at) arm.linux.org.uk> 24 25 Permission is hereby granted, free of charge, to any person obtaining a 26 copy of this software and associated documentation files (the "Software"), 27 to deal in the Software without restriction, including without limitation 28 the rights to use, copy, modify, merge, publish, distribute, sub license, 29 and/or sell copies of the Software, and to permit persons to whom the 30 Software is furnished to do so, subject to the following conditions: 31 32 The above copyright notice and this permission notice (including the 33 next paragraph) shall be included in all copies or substantial portions 34 of the Software. 35 36 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 37 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 38 FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 39 THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 40 LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 41 FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 42 DEALINGS IN THE SOFTWARE. 43 */ 44 45 46 #define COMPARE_FUNC_NEVER 0x00000000 47 #define COMPARE_FUNC_LESS 0x00000001 48 #define COMPARE_FUNC_EQUAL 0x00000002 49 #define COMPARE_FUNC_LEQUAL 0x00000003 50 #define COMPARE_FUNC_GREATER 0x00000004 51 #define COMPARE_FUNC_NOTEQUAL 0x00000005 52 #define COMPARE_FUNC_GEQUAL 0x00000006 53 #define COMPARE_FUNC_ALWAYS 0x00000007 54 #define STENCIL_OP_KEEP 0x00000000 55 #define STENCIL_OP_ZERO 0x00000001 56 #define STENCIL_OP_REPLACE 0x00000002 57 #define STENCIL_OP_INCR 0x00000003 58 #define STENCIL_OP_DECR 0x00000004 59 #define STENCIL_OP_INVERT 0x00000005 60 #define STENCIL_OP_INCR_WRAP 0x00000006 61 #define STENCIL_OP_DECR_WRAP 0x00000007 62 #define BLEND_EQ_ADD 0x00000000 63 #define BLEND_EQ_SUBTRACT 0x00000001 64 #define BLEND_EQ_REVERSE_SUBTRACT 0x00000002 65 #define BLEND_EQ_MIN 0x00000003 66 #define BLEND_EQ_MAX 0x00000004 67 #define BLEND_FUNC_ZERO 0x00000000 68 #define BLEND_FUNC_ONE 0x00000001 69 #define BLEND_FUNC_SRC_COLOR 0x00000002 70 #define BLEND_FUNC_ONE_MINUS_SRC_COLOR 0x00000003 71 #define BLEND_FUNC_SRC_ALPHA 0x00000004 72 #define BLEND_FUNC_ONE_MINUS_SRC_ALPHA 0x00000005 73 #define BLEND_FUNC_DST_ALPHA 0x00000006 74 #define BLEND_FUNC_ONE_MINUS_DST_ALPHA 0x00000007 75 #define BLEND_FUNC_DST_COLOR 0x00000008 76 #define BLEND_FUNC_ONE_MINUS_DST_COLOR 0x00000009 77 #define BLEND_FUNC_SRC_ALPHA_SATURATE 0x0000000a 78 #define BLEND_FUNC_CONSTANT_ALPHA 0x0000000b 79 #define BLEND_FUNC_ONE_MINUS_CONSTANT_ALPHA 0x0000000c 80 #define BLEND_FUNC_CONSTANT_COLOR 0x0000000d 81 #define BLEND_FUNC_ONE_MINUS_CONSTANT_COLOR 0x0000000e 82 #define RS_FORMAT_X4R4G4B4 0x00000000 83 #define RS_FORMAT_A4R4G4B4 0x00000001 84 #define RS_FORMAT_X1R5G5B5 0x00000002 85 #define RS_FORMAT_A1R5G5B5 0x00000003 86 #define RS_FORMAT_R5G6B5 0x00000004 87 #define RS_FORMAT_X8R8G8B8 0x00000005 88 #define RS_FORMAT_A8R8G8B8 0x00000006 89 #define RS_FORMAT_YUY2 0x00000007 90 #define TEXTURE_FORMAT_NONE 0x00000000 91 #define TEXTURE_FORMAT_A8 0x00000001 92 #define TEXTURE_FORMAT_L8 0x00000002 93 #define TEXTURE_FORMAT_I8 0x00000003 94 #define TEXTURE_FORMAT_A8L8 0x00000004 95 #define TEXTURE_FORMAT_A4R4G4B4 0x00000005 96 #define TEXTURE_FORMAT_X4R4G4B4 0x00000006 97 #define TEXTURE_FORMAT_A8R8G8B8 0x00000007 98 #define TEXTURE_FORMAT_X8R8G8B8 0x00000008 99 #define TEXTURE_FORMAT_A8B8G8R8 0x00000009 100 #define TEXTURE_FORMAT_X8B8G8R8 0x0000000a 101 #define TEXTURE_FORMAT_R5G6B5 0x0000000b 102 #define TEXTURE_FORMAT_A1R5G5B5 0x0000000c 103 #define TEXTURE_FORMAT_X1R5G5B5 0x0000000d 104 #define TEXTURE_FORMAT_YUY2 0x0000000e 105 #define TEXTURE_FORMAT_UYVY 0x0000000f 106 #define TEXTURE_FORMAT_D16 0x00000010 107 #define TEXTURE_FORMAT_D24S8 0x00000011 108 #define TEXTURE_FORMAT_DXT1 0x00000013 109 #define TEXTURE_FORMAT_DXT2_DXT3 0x00000014 110 #define TEXTURE_FORMAT_DXT4_DXT5 0x00000015 111 #define TEXTURE_FORMAT_ETC1 0x0000001e 112 #define TEXTURE_FORMAT_EXT_NONE 0x00000000 113 #define TEXTURE_FORMAT_EXT_A16F 0x00000007 114 #define TEXTURE_FORMAT_EXT_A16L16F 0x00000008 115 #define TEXTURE_FORMAT_EXT_A16B16G16R16F 0x00000009 116 #define TEXTURE_FORMAT_EXT_A32F 0x0000000a 117 #define TEXTURE_FORMAT_EXT_A32L32F 0x0000000b 118 #define TEXTURE_FORMAT_EXT_A2B10G10R10 0x0000000c 119 #define TEXTURE_FILTER_NONE 0x00000000 120 #define TEXTURE_FILTER_NEAREST 0x00000001 121 #define TEXTURE_FILTER_LINEAR 0x00000002 122 #define TEXTURE_FILTER_ANISOTROPIC 0x00000003 123 #define TEXTURE_TYPE_NONE 0x00000000 124 #define TEXTURE_TYPE_2D 0x00000002 125 #define TEXTURE_TYPE_CUBE_MAP 0x00000005 126 #define TEXTURE_WRAPMODE_REPEAT 0x00000000 127 #define TEXTURE_WRAPMODE_MIRRORED_REPEAT 0x00000001 128 #define TEXTURE_WRAPMODE_CLAMP_TO_EDGE 0x00000002 129 #define TEXTURE_FACE_POS_X 0x00000000 130 #define TEXTURE_FACE_NEG_X 0x00000001 131 #define TEXTURE_FACE_POS_Y 0x00000002 132 #define TEXTURE_FACE_NEG_Y 0x00000003 133 #define TEXTURE_FACE_POS_Z 0x00000004 134 #define TEXTURE_FACE_NEG_Z 0x00000005 135 #define TEXTURE_SWIZZLE_RED 0x00000000 136 #define TEXTURE_SWIZZLE_GREEN 0x00000001 137 #define TEXTURE_SWIZZLE_BLUE 0x00000002 138 #define TEXTURE_SWIZZLE_ALPHA 0x00000003 139 #define TEXTURE_SWIZZLE_ZERO 0x00000004 140 #define TEXTURE_SWIZZLE_ONE 0x00000005 141 #define TEXTURE_HALIGN_FOUR 0x00000000 142 #define TEXTURE_HALIGN_SIXTEEN 0x00000001 143 #define TEXTURE_HALIGN_SUPER_TILED 0x00000002 144 #define TEXTURE_HALIGN_SPLIT_TILED 0x00000003 145 #define TEXTURE_HALIGN_SPLIT_SUPER_TILED 0x00000004 146 #define LOGIC_OP_CLEAR 0x00000000 147 #define LOGIC_OP_NOR 0x00000001 148 #define LOGIC_OP_AND_INVERTED 0x00000002 149 #define LOGIC_OP_COPY_INVERTED 0x00000003 150 #define LOGIC_OP_AND_REVERSE 0x00000004 151 #define LOGIC_OP_INVERT 0x00000005 152 #define LOGIC_OP_XOR 0x00000006 153 #define LOGIC_OP_NAND 0x00000007 154 #define LOGIC_OP_AND 0x00000008 155 #define LOGIC_OP_EQUIV 0x00000009 156 #define LOGIC_OP_NOOP 0x0000000a 157 #define LOGIC_OP_OR_INVERTED 0x0000000b 158 #define LOGIC_OP_COPY 0x0000000c 159 #define LOGIC_OP_OR_REVERSE 0x0000000d 160 #define LOGIC_OP_OR 0x0000000e 161 #define LOGIC_OP_SET 0x0000000f 162 #define VIVS_VS 0x00000000 163 164 #define VIVS_VS_END_PC 0x00000800 165 166 #define VIVS_VS_OUTPUT_COUNT 0x00000804 167 168 #define VIVS_VS_INPUT_COUNT 0x00000808 169 #define VIVS_VS_INPUT_COUNT_COUNT__MASK 0x0000000f 170 #define VIVS_VS_INPUT_COUNT_COUNT__SHIFT 0 171 #define VIVS_VS_INPUT_COUNT_COUNT(x) (((x) << VIVS_VS_INPUT_COUNT_COUNT__SHIFT) & VIVS_VS_INPUT_COUNT_COUNT__MASK) 172 #define VIVS_VS_INPUT_COUNT_UNK8__MASK 0x00001f00 173 #define VIVS_VS_INPUT_COUNT_UNK8__SHIFT 8 174 #define VIVS_VS_INPUT_COUNT_UNK8(x) (((x) << VIVS_VS_INPUT_COUNT_UNK8__SHIFT) & VIVS_VS_INPUT_COUNT_UNK8__MASK) 175 176 #define VIVS_VS_TEMP_REGISTER_CONTROL 0x0000080c 177 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f 178 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 179 #define VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_VS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) 180 181 #define VIVS_VS_OUTPUT(i0) (0x00000810 + 0x4*(i0)) 182 #define VIVS_VS_OUTPUT__ESIZE 0x00000004 183 #define VIVS_VS_OUTPUT__LEN 0x00000004 184 #define VIVS_VS_OUTPUT_O0__MASK 0x000000ff 185 #define VIVS_VS_OUTPUT_O0__SHIFT 0 186 #define VIVS_VS_OUTPUT_O0(x) (((x) << VIVS_VS_OUTPUT_O0__SHIFT) & VIVS_VS_OUTPUT_O0__MASK) 187 #define VIVS_VS_OUTPUT_O1__MASK 0x0000ff00 188 #define VIVS_VS_OUTPUT_O1__SHIFT 8 189 #define VIVS_VS_OUTPUT_O1(x) (((x) << VIVS_VS_OUTPUT_O1__SHIFT) & VIVS_VS_OUTPUT_O1__MASK) 190 #define VIVS_VS_OUTPUT_O2__MASK 0x00ff0000 191 #define VIVS_VS_OUTPUT_O2__SHIFT 16 192 #define VIVS_VS_OUTPUT_O2(x) (((x) << VIVS_VS_OUTPUT_O2__SHIFT) & VIVS_VS_OUTPUT_O2__MASK) 193 #define VIVS_VS_OUTPUT_O3__MASK 0xff000000 194 #define VIVS_VS_OUTPUT_O3__SHIFT 24 195 #define VIVS_VS_OUTPUT_O3(x) (((x) << VIVS_VS_OUTPUT_O3__SHIFT) & VIVS_VS_OUTPUT_O3__MASK) 196 197 #define VIVS_VS_INPUT(i0) (0x00000820 + 0x4*(i0)) 198 #define VIVS_VS_INPUT__ESIZE 0x00000004 199 #define VIVS_VS_INPUT__LEN 0x00000004 200 #define VIVS_VS_INPUT_I0__MASK 0x000000ff 201 #define VIVS_VS_INPUT_I0__SHIFT 0 202 #define VIVS_VS_INPUT_I0(x) (((x) << VIVS_VS_INPUT_I0__SHIFT) & VIVS_VS_INPUT_I0__MASK) 203 #define VIVS_VS_INPUT_I1__MASK 0x0000ff00 204 #define VIVS_VS_INPUT_I1__SHIFT 8 205 #define VIVS_VS_INPUT_I1(x) (((x) << VIVS_VS_INPUT_I1__SHIFT) & VIVS_VS_INPUT_I1__MASK) 206 #define VIVS_VS_INPUT_I2__MASK 0x00ff0000 207 #define VIVS_VS_INPUT_I2__SHIFT 16 208 #define VIVS_VS_INPUT_I2(x) (((x) << VIVS_VS_INPUT_I2__SHIFT) & VIVS_VS_INPUT_I2__MASK) 209 #define VIVS_VS_INPUT_I3__MASK 0xff000000 210 #define VIVS_VS_INPUT_I3__SHIFT 24 211 #define VIVS_VS_INPUT_I3(x) (((x) << VIVS_VS_INPUT_I3__SHIFT) & VIVS_VS_INPUT_I3__MASK) 212 213 #define VIVS_VS_LOAD_BALANCING 0x00000830 214 #define VIVS_VS_LOAD_BALANCING_A__MASK 0x000000ff 215 #define VIVS_VS_LOAD_BALANCING_A__SHIFT 0 216 #define VIVS_VS_LOAD_BALANCING_A(x) (((x) << VIVS_VS_LOAD_BALANCING_A__SHIFT) & VIVS_VS_LOAD_BALANCING_A__MASK) 217 #define VIVS_VS_LOAD_BALANCING_B__MASK 0x0000ff00 218 #define VIVS_VS_LOAD_BALANCING_B__SHIFT 8 219 #define VIVS_VS_LOAD_BALANCING_B(x) (((x) << VIVS_VS_LOAD_BALANCING_B__SHIFT) & VIVS_VS_LOAD_BALANCING_B__MASK) 220 #define VIVS_VS_LOAD_BALANCING_C__MASK 0x00ff0000 221 #define VIVS_VS_LOAD_BALANCING_C__SHIFT 16 222 #define VIVS_VS_LOAD_BALANCING_C(x) (((x) << VIVS_VS_LOAD_BALANCING_C__SHIFT) & VIVS_VS_LOAD_BALANCING_C__MASK) 223 #define VIVS_VS_LOAD_BALANCING_D__MASK 0xff000000 224 #define VIVS_VS_LOAD_BALANCING_D__SHIFT 24 225 #define VIVS_VS_LOAD_BALANCING_D(x) (((x) << VIVS_VS_LOAD_BALANCING_D__SHIFT) & VIVS_VS_LOAD_BALANCING_D__MASK) 226 227 #define VIVS_VS_PERF_COUNTER 0x00000834 228 229 #define VIVS_VS_START_PC 0x00000838 230 231 #define VIVS_VS_UNK00850 0x00000850 232 233 #define VIVS_VS_UNK00854 0x00000854 234 235 #define VIVS_VS_UNK00858 0x00000858 236 237 #define VIVS_VS_RANGE 0x0000085c 238 #define VIVS_VS_RANGE_LOW__MASK 0x0000ffff 239 #define VIVS_VS_RANGE_LOW__SHIFT 0 240 #define VIVS_VS_RANGE_LOW(x) (((x) << VIVS_VS_RANGE_LOW__SHIFT) & VIVS_VS_RANGE_LOW__MASK) 241 #define VIVS_VS_RANGE_HIGH__MASK 0xffff0000 242 #define VIVS_VS_RANGE_HIGH__SHIFT 16 243 #define VIVS_VS_RANGE_HIGH(x) (((x) << VIVS_VS_RANGE_HIGH__SHIFT) & VIVS_VS_RANGE_HIGH__MASK) 244 245 #define VIVS_VS_NEW_UNK00860 0x00000860 246 247 #define VIVS_VS_UNK00864 0x00000864 248 249 #define VIVS_VS_UNK00868 0x00000868 250 251 #define VIVS_VS_UNK0086C 0x0000086c 252 253 #define VIVS_VS_INST_MEM(i0) (0x00004000 + 0x4*(i0)) 254 #define VIVS_VS_INST_MEM__ESIZE 0x00000004 255 #define VIVS_VS_INST_MEM__LEN 0x00000400 256 257 #define VIVS_VS_UNIFORMS(i0) (0x00005000 + 0x4*(i0)) 258 #define VIVS_VS_UNIFORMS__ESIZE 0x00000004 259 #define VIVS_VS_UNIFORMS__LEN 0x00000400 260 261 #define VIVS_CL 0x00000000 262 263 #define VIVS_CL_CONFIG 0x00000900 264 #define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003 265 #define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0 266 #define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK) 267 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070 268 #define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4 269 #define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK) 270 #define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100 271 #define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200 272 #define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400 273 #define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000 274 #define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12 275 #define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK) 276 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000 277 #define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16 278 #define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK) 279 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000 280 #define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20 281 #define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK) 282 #define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000 283 #define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24 284 #define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK) 285 286 #define VIVS_CL_GLOBAL_X 0x00000904 287 #define VIVS_CL_GLOBAL_X_SIZE__MASK 0x0000ffff 288 #define VIVS_CL_GLOBAL_X_SIZE__SHIFT 0 289 #define VIVS_CL_GLOBAL_X_SIZE(x) (((x) << VIVS_CL_GLOBAL_X_SIZE__SHIFT) & VIVS_CL_GLOBAL_X_SIZE__MASK) 290 #define VIVS_CL_GLOBAL_X_OFFSET__MASK 0xffff0000 291 #define VIVS_CL_GLOBAL_X_OFFSET__SHIFT 16 292 #define VIVS_CL_GLOBAL_X_OFFSET(x) (((x) << VIVS_CL_GLOBAL_X_OFFSET__SHIFT) & VIVS_CL_GLOBAL_X_OFFSET__MASK) 293 294 #define VIVS_CL_GLOBAL_Y 0x00000908 295 #define VIVS_CL_GLOBAL_Y_SIZE__MASK 0x0000ffff 296 #define VIVS_CL_GLOBAL_Y_SIZE__SHIFT 0 297 #define VIVS_CL_GLOBAL_Y_SIZE(x) (((x) << VIVS_CL_GLOBAL_Y_SIZE__SHIFT) & VIVS_CL_GLOBAL_Y_SIZE__MASK) 298 #define VIVS_CL_GLOBAL_Y_OFFSET__MASK 0xffff0000 299 #define VIVS_CL_GLOBAL_Y_OFFSET__SHIFT 16 300 #define VIVS_CL_GLOBAL_Y_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Y_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Y_OFFSET__MASK) 301 302 #define VIVS_CL_GLOBAL_Z 0x0000090c 303 #define VIVS_CL_GLOBAL_Z_SIZE__MASK 0x0000ffff 304 #define VIVS_CL_GLOBAL_Z_SIZE__SHIFT 0 305 #define VIVS_CL_GLOBAL_Z_SIZE(x) (((x) << VIVS_CL_GLOBAL_Z_SIZE__SHIFT) & VIVS_CL_GLOBAL_Z_SIZE__MASK) 306 #define VIVS_CL_GLOBAL_Z_OFFSET__MASK 0xffff0000 307 #define VIVS_CL_GLOBAL_Z_OFFSET__SHIFT 16 308 #define VIVS_CL_GLOBAL_Z_OFFSET(x) (((x) << VIVS_CL_GLOBAL_Z_OFFSET__SHIFT) & VIVS_CL_GLOBAL_Z_OFFSET__MASK) 309 310 #define VIVS_CL_WORKGROUP_X 0x00000910 311 #define VIVS_CL_WORKGROUP_X_SIZE__MASK 0x000003ff 312 #define VIVS_CL_WORKGROUP_X_SIZE__SHIFT 0 313 #define VIVS_CL_WORKGROUP_X_SIZE(x) (((x) << VIVS_CL_WORKGROUP_X_SIZE__SHIFT) & VIVS_CL_WORKGROUP_X_SIZE__MASK) 314 #define VIVS_CL_WORKGROUP_X_COUNT__MASK 0xffff0000 315 #define VIVS_CL_WORKGROUP_X_COUNT__SHIFT 16 316 #define VIVS_CL_WORKGROUP_X_COUNT(x) (((x) << VIVS_CL_WORKGROUP_X_COUNT__SHIFT) & VIVS_CL_WORKGROUP_X_COUNT__MASK) 317 318 #define VIVS_CL_WORKGROUP_Y 0x00000914 319 #define VIVS_CL_WORKGROUP_Y_SIZE__MASK 0x000003ff 320 #define VIVS_CL_WORKGROUP_Y_SIZE__SHIFT 0 321 #define VIVS_CL_WORKGROUP_Y_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Y_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Y_SIZE__MASK) 322 #define VIVS_CL_WORKGROUP_Y_COUNT__MASK 0xffff0000 323 #define VIVS_CL_WORKGROUP_Y_COUNT__SHIFT 16 324 #define VIVS_CL_WORKGROUP_Y_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Y_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Y_COUNT__MASK) 325 326 #define VIVS_CL_WORKGROUP_Z 0x00000918 327 #define VIVS_CL_WORKGROUP_Z_SIZE__MASK 0x000003ff 328 #define VIVS_CL_WORKGROUP_Z_SIZE__SHIFT 0 329 #define VIVS_CL_WORKGROUP_Z_SIZE(x) (((x) << VIVS_CL_WORKGROUP_Z_SIZE__SHIFT) & VIVS_CL_WORKGROUP_Z_SIZE__MASK) 330 #define VIVS_CL_WORKGROUP_Z_COUNT__MASK 0xffff0000 331 #define VIVS_CL_WORKGROUP_Z_COUNT__SHIFT 16 332 #define VIVS_CL_WORKGROUP_Z_COUNT(x) (((x) << VIVS_CL_WORKGROUP_Z_COUNT__SHIFT) & VIVS_CL_WORKGROUP_Z_COUNT__MASK) 333 334 #define VIVS_CL_THREAD_ALLOCATION 0x0000091c 335 336 #define VIVS_CL_KICKER 0x00000920 337 338 #define VIVS_CL_UNK00924 0x00000924 339 340 #define VIVS_PA 0x00000000 341 342 #define VIVS_PA_VIEWPORT_SCALE_X 0x00000a00 343 344 #define VIVS_PA_VIEWPORT_SCALE_Y 0x00000a04 345 346 #define VIVS_PA_VIEWPORT_SCALE_Z 0x00000a08 347 348 #define VIVS_PA_VIEWPORT_OFFSET_X 0x00000a0c 349 350 #define VIVS_PA_VIEWPORT_OFFSET_Y 0x00000a10 351 352 #define VIVS_PA_VIEWPORT_OFFSET_Z 0x00000a14 353 354 #define VIVS_PA_LINE_WIDTH 0x00000a18 355 356 #define VIVS_PA_POINT_SIZE 0x00000a1c 357 358 #define VIVS_PA_SYSTEM_MODE 0x00000a28 359 #define VIVS_PA_SYSTEM_MODE_UNK0 0x00000001 360 #define VIVS_PA_SYSTEM_MODE_UNK4 0x00000010 361 362 #define VIVS_PA_W_CLIP_LIMIT 0x00000a2c 363 364 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT 0x00000a30 365 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK 0x000000ff 366 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT 0 367 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_UNK0__MASK) 368 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK 0x0000ff00 369 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT 8 370 #define VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT(x) (((x) << VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__SHIFT) & VIVS_PA_ATTRIBUTE_ELEMENT_COUNT_COUNT__MASK) 371 372 #define VIVS_PA_CONFIG 0x00000a34 373 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE 0x00000004 374 #define VIVS_PA_CONFIG_POINT_SIZE_ENABLE_MASK 0x00000008 375 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE 0x00000010 376 #define VIVS_PA_CONFIG_POINT_SPRITE_ENABLE_MASK 0x00000020 377 #define VIVS_PA_CONFIG_CULL_FACE_MODE__MASK 0x00000300 378 #define VIVS_PA_CONFIG_CULL_FACE_MODE__SHIFT 8 379 #define VIVS_PA_CONFIG_CULL_FACE_MODE_OFF 0x00000000 380 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CW 0x00000100 381 #define VIVS_PA_CONFIG_CULL_FACE_MODE_CCW 0x00000200 382 #define VIVS_PA_CONFIG_CULL_FACE_MODE_MASK 0x00000400 383 #define VIVS_PA_CONFIG_FILL_MODE__MASK 0x00003000 384 #define VIVS_PA_CONFIG_FILL_MODE__SHIFT 12 385 #define VIVS_PA_CONFIG_FILL_MODE_POINT 0x00000000 386 #define VIVS_PA_CONFIG_FILL_MODE_WIREFRAME 0x00001000 387 #define VIVS_PA_CONFIG_FILL_MODE_SOLID 0x00002000 388 #define VIVS_PA_CONFIG_FILL_MODE_MASK 0x00004000 389 #define VIVS_PA_CONFIG_SHADE_MODEL__MASK 0x00030000 390 #define VIVS_PA_CONFIG_SHADE_MODEL__SHIFT 16 391 #define VIVS_PA_CONFIG_SHADE_MODEL_FLAT 0x00000000 392 #define VIVS_PA_CONFIG_SHADE_MODEL_SMOOTH 0x00010000 393 #define VIVS_PA_CONFIG_SHADE_MODEL_MASK 0x00040000 394 #define VIVS_PA_CONFIG_WIDE_LINE 0x00400000 395 #define VIVS_PA_CONFIG_WIDE_LINE_MASK 0x00800000 396 397 #define VIVS_PA_WIDE_LINE_WIDTH0 0x00000a38 398 399 #define VIVS_PA_WIDE_LINE_WIDTH1 0x00000a3c 400 401 #define VIVS_PA_SHADER_ATTRIBUTES(i0) (0x00000a40 + 0x4*(i0)) 402 #define VIVS_PA_SHADER_ATTRIBUTES__ESIZE 0x00000004 403 #define VIVS_PA_SHADER_ATTRIBUTES__LEN 0x0000000a 404 #define VIVS_PA_SHADER_ATTRIBUTES_BYPASS_FLAT 0x00000001 405 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK 0x000000f0 406 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT 4 407 #define VIVS_PA_SHADER_ATTRIBUTES_UNK4(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK4__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK4__MASK) 408 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK 0x00000f00 409 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT 8 410 #define VIVS_PA_SHADER_ATTRIBUTES_UNK8(x) (((x) << VIVS_PA_SHADER_ATTRIBUTES_UNK8__SHIFT) & VIVS_PA_SHADER_ATTRIBUTES_UNK8__MASK) 411 412 #define VIVS_PA_VIEWPORT_UNK00A80 0x00000a80 413 414 #define VIVS_PA_VIEWPORT_UNK00A84 0x00000a84 415 416 #define VIVS_PA_FLAGS 0x00000a88 417 #define VIVS_PA_FLAGS_UNK24 0x01000000 418 #define VIVS_PA_FLAGS_ZCONVERT_BYPASS 0x40000000 419 420 #define VIVS_PA_ZFARCLIPPING 0x00000a8c 421 422 #define VIVS_SE 0x00000000 423 424 #define VIVS_SE_SCISSOR_LEFT 0x00000c00 425 426 #define VIVS_SE_SCISSOR_TOP 0x00000c04 427 428 #define VIVS_SE_SCISSOR_RIGHT 0x00000c08 429 430 #define VIVS_SE_SCISSOR_BOTTOM 0x00000c0c 431 432 #define VIVS_SE_DEPTH_SCALE 0x00000c10 433 434 #define VIVS_SE_DEPTH_BIAS 0x00000c14 435 436 #define VIVS_SE_CONFIG 0x00000c18 437 #define VIVS_SE_CONFIG_LAST_PIXEL_ENABLE 0x00000001 438 439 #define VIVS_SE_UNK00C1C 0x00000c1c 440 441 #define VIVS_SE_CLIP_RIGHT 0x00000c20 442 443 #define VIVS_SE_CLIP_BOTTOM 0x00000c24 444 445 #define VIVS_RA 0x00000000 446 447 #define VIVS_RA_CONTROL 0x00000e00 448 #define VIVS_RA_CONTROL_UNK0 0x00000001 449 #define VIVS_RA_CONTROL_LAST_VARYING_2X 0x00000002 450 451 #define VIVS_RA_MULTISAMPLE_UNK00E04 0x00000e04 452 453 #define VIVS_RA_EARLY_DEPTH 0x00000e08 454 455 #define VIVS_RA_UNK00E0C 0x00000e0c 456 457 #define VIVS_RA_MULTISAMPLE_UNK00E10(i0) (0x00000e10 + 0x4*(i0)) 458 #define VIVS_RA_MULTISAMPLE_UNK00E10__ESIZE 0x00000004 459 #define VIVS_RA_MULTISAMPLE_UNK00E10__LEN 0x00000004 460 461 #define VIVS_RA_HDEPTH_CONTROL 0x00000e20 462 #define VIVS_RA_HDEPTH_CONTROL_UNK0 0x00000001 463 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK 0x00007000 464 #define VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT 12 465 #define VIVS_RA_HDEPTH_CONTROL_COMPARE(x) (((x) << VIVS_RA_HDEPTH_CONTROL_COMPARE__SHIFT) & VIVS_RA_HDEPTH_CONTROL_COMPARE__MASK) 466 467 #define VIVS_RA_CENTROID_TABLE(i0) (0x00000e40 + 0x4*(i0)) 468 #define VIVS_RA_CENTROID_TABLE__ESIZE 0x00000004 469 #define VIVS_RA_CENTROID_TABLE__LEN 0x00000010 470 471 #define VIVS_PS 0x00000000 472 473 #define VIVS_PS_END_PC 0x00001000 474 475 #define VIVS_PS_OUTPUT_REG 0x00001004 476 477 #define VIVS_PS_INPUT_COUNT 0x00001008 478 #define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000000f 479 #define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0 480 #define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK) 481 #define VIVS_PS_INPUT_COUNT_UNK8__MASK 0x00001f00 482 #define VIVS_PS_INPUT_COUNT_UNK8__SHIFT 8 483 #define VIVS_PS_INPUT_COUNT_UNK8(x) (((x) << VIVS_PS_INPUT_COUNT_UNK8__SHIFT) & VIVS_PS_INPUT_COUNT_UNK8__MASK) 484 485 #define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c 486 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f 487 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0 488 #define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK) 489 490 #define VIVS_PS_CONTROL 0x00001010 491 #define VIVS_PS_CONTROL_BYPASS 0x00000001 492 #define VIVS_PS_CONTROL_UNK1 0x00000002 493 494 #define VIVS_PS_PERF_COUNTER 0x00001014 495 496 #define VIVS_PS_START_PC 0x00001018 497 498 #define VIVS_PS_RANGE 0x0000101c 499 #define VIVS_PS_RANGE_LOW__MASK 0x0000ffff 500 #define VIVS_PS_RANGE_LOW__SHIFT 0 501 #define VIVS_PS_RANGE_LOW(x) (((x) << VIVS_PS_RANGE_LOW__SHIFT) & VIVS_PS_RANGE_LOW__MASK) 502 #define VIVS_PS_RANGE_HIGH__MASK 0xffff0000 503 #define VIVS_PS_RANGE_HIGH__SHIFT 16 504 #define VIVS_PS_RANGE_HIGH(x) (((x) << VIVS_PS_RANGE_HIGH__SHIFT) & VIVS_PS_RANGE_HIGH__MASK) 505 506 #define VIVS_PS_UNK01024 0x00001024 507 508 #define VIVS_PS_UNK01028 0x00001028 509 510 #define VIVS_PS_UNK01030 0x00001030 511 512 #define VIVS_PS_INST_MEM(i0) (0x00006000 + 0x4*(i0)) 513 #define VIVS_PS_INST_MEM__ESIZE 0x00000004 514 #define VIVS_PS_INST_MEM__LEN 0x00000400 515 516 #define VIVS_PS_UNIFORMS(i0) (0x00007000 + 0x4*(i0)) 517 #define VIVS_PS_UNIFORMS__ESIZE 0x00000004 518 #define VIVS_PS_UNIFORMS__LEN 0x00000400 519 520 #define VIVS_PE 0x00000000 521 522 #define VIVS_PE_DEPTH_CONFIG 0x00001400 523 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__MASK 0x00000003 524 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE__SHIFT 0 525 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_NONE 0x00000000 526 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_Z 0x00000001 527 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_W 0x00000002 528 #define VIVS_PE_DEPTH_CONFIG_DEPTH_MODE_MASK 0x00000008 529 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__MASK 0x00000010 530 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT__SHIFT 4 531 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D16 0x00000000 532 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_D24S8 0x00000010 533 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FORMAT_MASK 0x00000020 534 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK 0x00000700 535 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT 8 536 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC(x) (((x) << VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__SHIFT) & VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC__MASK) 537 #define VIVS_PE_DEPTH_CONFIG_DEPTH_FUNC_MASK 0x00000800 538 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE 0x00001000 539 #define VIVS_PE_DEPTH_CONFIG_WRITE_ENABLE_MASK 0x00002000 540 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z 0x00010000 541 #define VIVS_PE_DEPTH_CONFIG_EARLY_Z_MASK 0x00020000 542 #define VIVS_PE_DEPTH_CONFIG_UNK18 0x00040000 543 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH 0x00100000 544 #define VIVS_PE_DEPTH_CONFIG_ONLY_DEPTH_MASK 0x00200000 545 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS 0x01000000 546 #define VIVS_PE_DEPTH_CONFIG_DISABLE_ZS_MASK 0x02000000 547 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED 0x04000000 548 #define VIVS_PE_DEPTH_CONFIG_SUPER_TILED_MASK 0x08000000 549 550 #define VIVS_PE_DEPTH_NEAR 0x00001404 551 552 #define VIVS_PE_DEPTH_FAR 0x00001408 553 554 #define VIVS_PE_DEPTH_NORMALIZE 0x0000140c 555 556 #define VIVS_PE_DEPTH_ADDR 0x00001410 557 558 #define VIVS_PE_DEPTH_STRIDE 0x00001414 559 560 #define VIVS_PE_STENCIL_OP 0x00001418 561 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK 0x00000007 562 #define VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT 0 563 #define VIVS_PE_STENCIL_OP_FUNC_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_FRONT__MASK) 564 #define VIVS_PE_STENCIL_OP_FUNC_FRONT_MASK 0x00000008 565 #define VIVS_PE_STENCIL_OP_PASS_FRONT__MASK 0x00000070 566 #define VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT 4 567 #define VIVS_PE_STENCIL_OP_PASS_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_PASS_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_PASS_FRONT__MASK) 568 #define VIVS_PE_STENCIL_OP_PASS_FRONT_MASK 0x00000080 569 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK 0x00000700 570 #define VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT 8 571 #define VIVS_PE_STENCIL_OP_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_FRONT__MASK) 572 #define VIVS_PE_STENCIL_OP_FAIL_FRONT_MASK 0x00000800 573 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK 0x00007000 574 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT 12 575 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT__MASK) 576 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_FRONT_MASK 0x00008000 577 #define VIVS_PE_STENCIL_OP_FUNC_BACK__MASK 0x00070000 578 #define VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT 16 579 #define VIVS_PE_STENCIL_OP_FUNC_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FUNC_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FUNC_BACK__MASK) 580 #define VIVS_PE_STENCIL_OP_FUNC_BACK_MASK 0x00080000 581 #define VIVS_PE_STENCIL_OP_PASS_BACK__MASK 0x00700000 582 #define VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT 20 583 #define VIVS_PE_STENCIL_OP_PASS_BACK(x) (((x) << VIVS_PE_STENCIL_OP_PASS_BACK__SHIFT) & VIVS_PE_STENCIL_OP_PASS_BACK__MASK) 584 #define VIVS_PE_STENCIL_OP_PASS_BACK_MASK 0x00800000 585 #define VIVS_PE_STENCIL_OP_FAIL_BACK__MASK 0x07000000 586 #define VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT 24 587 #define VIVS_PE_STENCIL_OP_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_FAIL_BACK__MASK) 588 #define VIVS_PE_STENCIL_OP_FAIL_BACK_MASK 0x08000000 589 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK 0x70000000 590 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT 28 591 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK(x) (((x) << VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__SHIFT) & VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK__MASK) 592 #define VIVS_PE_STENCIL_OP_DEPTH_FAIL_BACK_MASK 0x80000000 593 594 #define VIVS_PE_STENCIL_CONFIG 0x0000141c 595 #define VIVS_PE_STENCIL_CONFIG_MODE__MASK 0x00000003 596 #define VIVS_PE_STENCIL_CONFIG_MODE__SHIFT 0 597 #define VIVS_PE_STENCIL_CONFIG_MODE_DISABLED 0x00000000 598 #define VIVS_PE_STENCIL_CONFIG_MODE_ONE_SIDED 0x00000001 599 #define VIVS_PE_STENCIL_CONFIG_MODE_TWO_SIDED 0x00000002 600 #define VIVS_PE_STENCIL_CONFIG_MODE_MASK 0x00000010 601 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT_MASK 0x00000020 602 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT_MASK 0x00000040 603 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_MASK 0x00000080 604 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK 0x0000ff00 605 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT 8 606 #define VIVS_PE_STENCIL_CONFIG_REF_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_REF_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_REF_FRONT__MASK) 607 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK 0x00ff0000 608 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT 16 609 #define VIVS_PE_STENCIL_CONFIG_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_MASK_FRONT__MASK) 610 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK 0xff000000 611 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT 24 612 #define VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT(x) (((x) << VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__SHIFT) & VIVS_PE_STENCIL_CONFIG_WRITE_MASK_FRONT__MASK) 613 614 #define VIVS_PE_ALPHA_OP 0x00001420 615 #define VIVS_PE_ALPHA_OP_ALPHA_TEST 0x00000001 616 #define VIVS_PE_ALPHA_OP_ALPHA_TEST_MASK 0x00000002 617 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK 0x00000070 618 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT 4 619 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_FUNC__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_FUNC__MASK) 620 #define VIVS_PE_ALPHA_OP_ALPHA_FUNC_MASK 0x00000080 621 #define VIVS_PE_ALPHA_OP_ALPHA_REF__MASK 0x0000ff00 622 #define VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT 8 623 #define VIVS_PE_ALPHA_OP_ALPHA_REF(x) (((x) << VIVS_PE_ALPHA_OP_ALPHA_REF__SHIFT) & VIVS_PE_ALPHA_OP_ALPHA_REF__MASK) 624 #define VIVS_PE_ALPHA_OP_ALPHA_REF_MASKFUNC_MASK 0x00010000 625 626 #define VIVS_PE_ALPHA_BLEND_COLOR 0x00001424 627 #define VIVS_PE_ALPHA_BLEND_COLOR_B__MASK 0x000000ff 628 #define VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT 0 629 #define VIVS_PE_ALPHA_BLEND_COLOR_B(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_B__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_B__MASK) 630 #define VIVS_PE_ALPHA_BLEND_COLOR_G__MASK 0x0000ff00 631 #define VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT 8 632 #define VIVS_PE_ALPHA_BLEND_COLOR_G(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_G__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_G__MASK) 633 #define VIVS_PE_ALPHA_BLEND_COLOR_R__MASK 0x00ff0000 634 #define VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT 16 635 #define VIVS_PE_ALPHA_BLEND_COLOR_R(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_R__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_R__MASK) 636 #define VIVS_PE_ALPHA_BLEND_COLOR_A__MASK 0xff000000 637 #define VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT 24 638 #define VIVS_PE_ALPHA_BLEND_COLOR_A(x) (((x) << VIVS_PE_ALPHA_BLEND_COLOR_A__SHIFT) & VIVS_PE_ALPHA_BLEND_COLOR_A__MASK) 639 640 #define VIVS_PE_ALPHA_CONFIG 0x00001428 641 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR 0x00000001 642 #define VIVS_PE_ALPHA_CONFIG_BLEND_ENABLE_COLOR_MASK 0x00000002 643 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR_MASK 0x00000004 644 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR_MASK 0x00000008 645 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK 0x000000f0 646 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT 4 647 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_COLOR__MASK) 648 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK 0x00000f00 649 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT 8 650 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_COLOR__MASK) 651 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK 0x00007000 652 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT 12 653 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_COLOR__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_COLOR__MASK) 654 #define VIVS_PE_ALPHA_CONFIG_EQ_COLOR_MASK 0x00008000 655 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA 0x00010000 656 #define VIVS_PE_ALPHA_CONFIG_BLEND_SEPARATE_ALPHA_MASK 0x00020000 657 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA_MASK 0x00040000 658 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA_MASK 0x00080000 659 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK 0x00f00000 660 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT 20 661 #define VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_SRC_FUNC_ALPHA__MASK) 662 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK 0x0f000000 663 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT 24 664 #define VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_DST_FUNC_ALPHA__MASK) 665 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK 0x70000000 666 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT 28 667 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA(x) (((x) << VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__SHIFT) & VIVS_PE_ALPHA_CONFIG_EQ_ALPHA__MASK) 668 #define VIVS_PE_ALPHA_CONFIG_EQ_ALPHA_MASK 0x80000000 669 670 #define VIVS_PE_COLOR_FORMAT 0x0000142c 671 #define VIVS_PE_COLOR_FORMAT_FORMAT__MASK 0x0000000f 672 #define VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT 0 673 #define VIVS_PE_COLOR_FORMAT_FORMAT(x) (((x) << VIVS_PE_COLOR_FORMAT_FORMAT__SHIFT) & VIVS_PE_COLOR_FORMAT_FORMAT__MASK) 674 #define VIVS_PE_COLOR_FORMAT_FORMAT_MASK 0x00000010 675 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK 0x00000f00 676 #define VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT 8 677 #define VIVS_PE_COLOR_FORMAT_COMPONENTS(x) (((x) << VIVS_PE_COLOR_FORMAT_COMPONENTS__SHIFT) & VIVS_PE_COLOR_FORMAT_COMPONENTS__MASK) 678 #define VIVS_PE_COLOR_FORMAT_COMPONENTS_MASK 0x00001000 679 #define VIVS_PE_COLOR_FORMAT_OVERWRITE 0x00010000 680 #define VIVS_PE_COLOR_FORMAT_OVERWRITE_MASK 0x00020000 681 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED 0x00100000 682 #define VIVS_PE_COLOR_FORMAT_SUPER_TILED_MASK 0x00200000 683 #define VIVS_PE_COLOR_FORMAT_UNK25 0x02000000 684 #define VIVS_PE_COLOR_FORMAT_UNK26 0x04000000 685 686 #define VIVS_PE_COLOR_ADDR 0x00001430 687 688 #define VIVS_PE_COLOR_STRIDE 0x00001434 689 690 #define VIVS_PE_HDEPTH_CONTROL 0x00001454 691 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__MASK 0x0000000f 692 #define VIVS_PE_HDEPTH_CONTROL_FORMAT__SHIFT 0 693 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_DISABLED 0x00000000 694 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D16 0x00000005 695 #define VIVS_PE_HDEPTH_CONTROL_FORMAT_D24S8 0x00000008 696 697 #define VIVS_PE_HDEPTH_ADDR 0x00001458 698 699 #define VIVS_PE_UNK0145C 0x0000145c 700 701 #define VIVS_PE_PIPE(i0) (0x00000000 + 0x4*(i0)) 702 #define VIVS_PE_PIPE__ESIZE 0x00000004 703 #define VIVS_PE_PIPE__LEN 0x00000008 704 705 #define VIVS_PE_PIPE_COLOR_ADDR(i0) (0x00001460 + 0x4*(i0)) 706 707 #define VIVS_PE_PIPE_DEPTH_ADDR(i0) (0x00001480 + 0x4*(i0)) 708 709 #define VIVS_PE_PIPE_ADDR_UNK01500(i0) (0x00001500 + 0x4*(i0)) 710 711 #define VIVS_PE_PIPE_ADDR_UNK01520(i0) (0x00001520 + 0x4*(i0)) 712 713 #define VIVS_PE_STENCIL_CONFIG_EXT 0x000014a0 714 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK 0x000000ff 715 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT 0 716 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK__MASK) 717 #define VIVS_PE_STENCIL_CONFIG_EXT_REF_BACK_MASK 0x00000100 718 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16_MASK 0x00000200 719 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK 0xffff0000 720 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT 16 721 #define VIVS_PE_STENCIL_CONFIG_EXT_UNK16(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT_UNK16__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT_UNK16__MASK) 722 723 #define VIVS_PE_LOGIC_OP 0x000014a4 724 #define VIVS_PE_LOGIC_OP_OP__MASK 0x0000000f 725 #define VIVS_PE_LOGIC_OP_OP__SHIFT 0 726 #define VIVS_PE_LOGIC_OP_OP(x) (((x) << VIVS_PE_LOGIC_OP_OP__SHIFT) & VIVS_PE_LOGIC_OP_OP__MASK) 727 #define VIVS_PE_LOGIC_OP_OP_MASK 0x00000010 728 729 #define VIVS_PE_DITHER(i0) (0x000014a8 + 0x4*(i0)) 730 #define VIVS_PE_DITHER__ESIZE 0x00000004 731 #define VIVS_PE_DITHER__LEN 0x00000002 732 733 #define VIVS_PE_ALPHA_COLOR_EXT0 0x000014b0 734 #define VIVS_PE_ALPHA_COLOR_EXT0_B__MASK 0x0000ffff 735 #define VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT 0 736 #define VIVS_PE_ALPHA_COLOR_EXT0_B(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_B__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_B__MASK) 737 #define VIVS_PE_ALPHA_COLOR_EXT0_G__MASK 0xffff0000 738 #define VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT 16 739 #define VIVS_PE_ALPHA_COLOR_EXT0_G(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT0_G__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT0_G__MASK) 740 741 #define VIVS_PE_ALPHA_COLOR_EXT1 0x000014b4 742 #define VIVS_PE_ALPHA_COLOR_EXT1_R__MASK 0x0000ffff 743 #define VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT 0 744 #define VIVS_PE_ALPHA_COLOR_EXT1_R(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_R__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_R__MASK) 745 #define VIVS_PE_ALPHA_COLOR_EXT1_A__MASK 0xffff0000 746 #define VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT 16 747 #define VIVS_PE_ALPHA_COLOR_EXT1_A(x) (((x) << VIVS_PE_ALPHA_COLOR_EXT1_A__SHIFT) & VIVS_PE_ALPHA_COLOR_EXT1_A__MASK) 748 749 #define VIVS_PE_STENCIL_CONFIG_EXT2 0x000014b8 750 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK 0x000000ff 751 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT 0 752 #define VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_MASK_BACK__MASK) 753 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK 0x0000ff00 754 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT 8 755 #define VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK(x) (((x) << VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__SHIFT) & VIVS_PE_STENCIL_CONFIG_EXT2_WRITE_MASK_BACK__MASK) 756 757 #define VIVS_PE_UNK01580(i0) (0x00001580 + 0x4*(i0)) 758 #define VIVS_PE_UNK01580__ESIZE 0x00000004 759 #define VIVS_PE_UNK01580__LEN 0x00000003 760 761 #define VIVS_CO 0x00000000 762 763 #define VIVS_CO_UNK03008 0x00003008 764 765 #define VIVS_CO_KICKER 0x0000300c 766 767 #define VIVS_CO_UNK03010 0x00003010 768 769 #define VIVS_CO_UNK03014 0x00003014 770 771 #define VIVS_CO_UNK03018 0x00003018 772 773 #define VIVS_CO_UNK0301C 0x0000301c 774 775 #define VIVS_CO_UNK03020 0x00003020 776 777 #define VIVS_CO_UNK03024 0x00003024 778 779 #define VIVS_CO_UNK03040 0x00003040 780 781 #define VIVS_CO_UNK03044 0x00003044 782 783 #define VIVS_CO_UNK03048 0x00003048 784 785 #define VIVS_CO_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 786 #define VIVS_CO_SAMPLER__ESIZE 0x00000004 787 #define VIVS_CO_SAMPLER__LEN 0x00000008 788 789 #define VIVS_CO_SAMPLER_UNK03060(i0) (0x00003060 + 0x4*(i0)) 790 791 #define VIVS_CO_SAMPLER_UNK03080(i0) (0x00003080 + 0x4*(i0)) 792 793 #define VIVS_CO_SAMPLER_UNK030A0(i0) (0x000030a0 + 0x4*(i0)) 794 795 #define VIVS_CO_SAMPLER_UNK030C0(i0) (0x000030c0 + 0x4*(i0)) 796 797 #define VIVS_CO_SAMPLER_UNK030E0(i0) (0x000030e0 + 0x4*(i0)) 798 799 #define VIVS_CO_SAMPLER_UNK03100(i0) (0x00003100 + 0x4*(i0)) 800 801 #define VIVS_CO_SAMPLER_UNK03120(i0) (0x00003120 + 0x4*(i0)) 802 803 #define VIVS_CO_SAMPLER_UNK03140(i0) (0x00003140 + 0x4*(i0)) 804 805 #define VIVS_CO_SAMPLER_UNK03160(i0) (0x00003160 + 0x4*(i0)) 806 807 #define VIVS_CO_SAMPLER_UNK03180(i0) (0x00003180 + 0x4*(i0)) 808 809 #define VIVS_CO_SAMPLER_UNK031A0(i0) (0x000031a0 + 0x4*(i0)) 810 811 #define VIVS_CO_SAMPLER_UNK031C0(i0) (0x000031c0 + 0x4*(i0)) 812 813 #define VIVS_CO_SAMPLER_UNK031E0(i0) (0x000031e0 + 0x4*(i0)) 814 815 #define VIVS_CO_ADDR_UNK03200(i0) (0x00003200 + 0x20*(i0)) 816 #define VIVS_CO_ADDR_UNK03200__ESIZE 0x00000020 817 #define VIVS_CO_ADDR_UNK03200__LEN 0x00000008 818 819 #define VIVS_CO_ADDR_UNK03200_PPIPE(i0, i1) (0x00003200 + 0x20*(i0) + 0x4*(i1)) 820 #define VIVS_CO_ADDR_UNK03200_PPIPE__ESIZE 0x00000004 821 #define VIVS_CO_ADDR_UNK03200_PPIPE__LEN 0x00000008 822 823 #define VIVS_RS 0x00000000 824 825 #define VIVS_RS_KICKER 0x00001600 826 827 #define VIVS_RS_CONFIG 0x00001604 828 #define VIVS_RS_CONFIG_SOURCE_FORMAT__MASK 0x0000001f 829 #define VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT 0 830 #define VIVS_RS_CONFIG_SOURCE_FORMAT(x) (((x) << VIVS_RS_CONFIG_SOURCE_FORMAT__SHIFT) & VIVS_RS_CONFIG_SOURCE_FORMAT__MASK) 831 #define VIVS_RS_CONFIG_DOWNSAMPLE_X 0x00000020 832 #define VIVS_RS_CONFIG_DOWNSAMPLE_Y 0x00000040 833 #define VIVS_RS_CONFIG_SOURCE_TILED 0x00000080 834 #define VIVS_RS_CONFIG_DEST_FORMAT__MASK 0x00001f00 835 #define VIVS_RS_CONFIG_DEST_FORMAT__SHIFT 8 836 #define VIVS_RS_CONFIG_DEST_FORMAT(x) (((x) << VIVS_RS_CONFIG_DEST_FORMAT__SHIFT) & VIVS_RS_CONFIG_DEST_FORMAT__MASK) 837 #define VIVS_RS_CONFIG_DEST_TILED 0x00004000 838 #define VIVS_RS_CONFIG_SWAP_RB 0x20000000 839 #define VIVS_RS_CONFIG_FLIP 0x40000000 840 841 #define VIVS_RS_SOURCE_ADDR 0x00001608 842 843 #define VIVS_RS_SOURCE_STRIDE 0x0000160c 844 #define VIVS_RS_SOURCE_STRIDE_STRIDE__MASK 0x0003ffff 845 #define VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT 0 846 #define VIVS_RS_SOURCE_STRIDE_STRIDE(x) (((x) << VIVS_RS_SOURCE_STRIDE_STRIDE__SHIFT) & VIVS_RS_SOURCE_STRIDE_STRIDE__MASK) 847 #define VIVS_RS_SOURCE_STRIDE_MULTI 0x40000000 848 #define VIVS_RS_SOURCE_STRIDE_TILING 0x80000000 849 850 #define VIVS_RS_DEST_ADDR 0x00001610 851 852 #define VIVS_RS_DEST_STRIDE 0x00001614 853 #define VIVS_RS_DEST_STRIDE_STRIDE__MASK 0x0003ffff 854 #define VIVS_RS_DEST_STRIDE_STRIDE__SHIFT 0 855 #define VIVS_RS_DEST_STRIDE_STRIDE(x) (((x) << VIVS_RS_DEST_STRIDE_STRIDE__SHIFT) & VIVS_RS_DEST_STRIDE_STRIDE__MASK) 856 #define VIVS_RS_DEST_STRIDE_MULTI 0x40000000 857 #define VIVS_RS_DEST_STRIDE_TILING 0x80000000 858 859 #define VIVS_RS_WINDOW_SIZE 0x00001620 860 #define VIVS_RS_WINDOW_SIZE_HEIGHT__MASK 0xffff0000 861 #define VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT 16 862 #define VIVS_RS_WINDOW_SIZE_HEIGHT(x) (((x) << VIVS_RS_WINDOW_SIZE_HEIGHT__SHIFT) & VIVS_RS_WINDOW_SIZE_HEIGHT__MASK) 863 #define VIVS_RS_WINDOW_SIZE_WIDTH__MASK 0x0000ffff 864 #define VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT 0 865 #define VIVS_RS_WINDOW_SIZE_WIDTH(x) (((x) << VIVS_RS_WINDOW_SIZE_WIDTH__SHIFT) & VIVS_RS_WINDOW_SIZE_WIDTH__MASK) 866 867 #define VIVS_RS_DITHER(i0) (0x00001630 + 0x4*(i0)) 868 #define VIVS_RS_DITHER__ESIZE 0x00000004 869 #define VIVS_RS_DITHER__LEN 0x00000002 870 871 #define VIVS_RS_CLEAR_CONTROL 0x0000163c 872 #define VIVS_RS_CLEAR_CONTROL_BITS__MASK 0x0000ffff 873 #define VIVS_RS_CLEAR_CONTROL_BITS__SHIFT 0 874 #define VIVS_RS_CLEAR_CONTROL_BITS(x) (((x) << VIVS_RS_CLEAR_CONTROL_BITS__SHIFT) & VIVS_RS_CLEAR_CONTROL_BITS__MASK) 875 #define VIVS_RS_CLEAR_CONTROL_MODE__MASK 0x00030000 876 #define VIVS_RS_CLEAR_CONTROL_MODE__SHIFT 16 877 #define VIVS_RS_CLEAR_CONTROL_MODE_DISABLED 0x00000000 878 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED1 0x00010000 879 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4 0x00020000 880 #define VIVS_RS_CLEAR_CONTROL_MODE_ENABLED4_2 0x00030000 881 882 #define VIVS_RS_FILL_VALUE(i0) (0x00001640 + 0x4*(i0)) 883 #define VIVS_RS_FILL_VALUE__ESIZE 0x00000004 884 #define VIVS_RS_FILL_VALUE__LEN 0x00000004 885 886 #define VIVS_RS_EXTRA_CONFIG 0x000016a0 887 #define VIVS_RS_EXTRA_CONFIG_AA__MASK 0x00000003 888 #define VIVS_RS_EXTRA_CONFIG_AA__SHIFT 0 889 #define VIVS_RS_EXTRA_CONFIG_AA(x) (((x) << VIVS_RS_EXTRA_CONFIG_AA__SHIFT) & VIVS_RS_EXTRA_CONFIG_AA__MASK) 890 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK 0x00000300 891 #define VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT 8 892 #define VIVS_RS_EXTRA_CONFIG_ENDIAN(x) (((x) << VIVS_RS_EXTRA_CONFIG_ENDIAN__SHIFT) & VIVS_RS_EXTRA_CONFIG_ENDIAN__MASK) 893 #define VIVS_RS_EXTRA_CONFIG_UNK20 0x00100000 894 #define VIVS_RS_EXTRA_CONFIG_UNK28 0x10000000 895 896 #define VIVS_RS_UNK016B0 0x000016b0 897 898 #define VIVS_RS_UNK016B4 0x000016b4 899 900 #define VIVS_RS_UNK016B8 0x000016b8 901 #define VIVS_RS_UNK016B8_UNK0 0x00000001 902 903 #define VIVS_RS_UNK016BC 0x000016bc 904 905 #define VIVS_RS_PIPE(i0) (0x00000000 + 0x4*(i0)) 906 #define VIVS_RS_PIPE__ESIZE 0x00000004 907 #define VIVS_RS_PIPE__LEN 0x00000008 908 909 #define VIVS_RS_PIPE_SOURCE_ADDR(i0) (0x000016c0 + 0x4*(i0)) 910 911 #define VIVS_RS_PIPE_DEST_ADDR(i0) (0x000016e0 + 0x4*(i0)) 912 913 #define VIVS_RS_PIPE_OFFSET(i0) (0x00001700 + 0x4*(i0)) 914 #define VIVS_RS_PIPE_OFFSET_X__MASK 0x0000ffff 915 #define VIVS_RS_PIPE_OFFSET_X__SHIFT 0 916 #define VIVS_RS_PIPE_OFFSET_X(x) (((x) << VIVS_RS_PIPE_OFFSET_X__SHIFT) & VIVS_RS_PIPE_OFFSET_X__MASK) 917 #define VIVS_RS_PIPE_OFFSET_Y__MASK 0xffff0000 918 #define VIVS_RS_PIPE_OFFSET_Y__SHIFT 16 919 #define VIVS_RS_PIPE_OFFSET_Y(x) (((x) << VIVS_RS_PIPE_OFFSET_Y__SHIFT) & VIVS_RS_PIPE_OFFSET_Y__MASK) 920 921 #define VIVS_TS 0x00000000 922 923 #define VIVS_TS_FLUSH_CACHE 0x00001650 924 #define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001 925 926 #define VIVS_TS_MEM_CONFIG 0x00001654 927 #define VIVS_TS_MEM_CONFIG_DEPTH_FAST_CLEAR 0x00000001 928 #define VIVS_TS_MEM_CONFIG_COLOR_FAST_CLEAR 0x00000002 929 #define VIVS_TS_MEM_CONFIG_DEPTH_16BPP 0x00000008 930 #define VIVS_TS_MEM_CONFIG_DEPTH_AUTO_DISABLE 0x00000010 931 #define VIVS_TS_MEM_CONFIG_COLOR_AUTO_DISABLE 0x00000020 932 #define VIVS_TS_MEM_CONFIG_DEPTH_COMPRESSION 0x00000040 933 #define VIVS_TS_MEM_CONFIG_MSAA 0x00000080 934 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__MASK 0x00000f00 935 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT__SHIFT 8 936 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A4R4G4B4 0x00000000 937 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A1R5G5B5 0x00000100 938 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_R5G6B5 0x00000200 939 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_A8R8G8B8 0x00000300 940 #define VIVS_TS_MEM_CONFIG_MSAA_FORMAT_X8R8G8B8 0x00000400 941 #define VIVS_TS_MEM_CONFIG_UNK12 0x00001000 942 #define VIVS_TS_MEM_CONFIG_HDEPTH_AUTO_DISABLE 0x00002000 943 944 #define VIVS_TS_COLOR_STATUS_BASE 0x00001658 945 946 #define VIVS_TS_COLOR_SURFACE_BASE 0x0000165c 947 948 #define VIVS_TS_COLOR_CLEAR_VALUE 0x00001660 949 950 #define VIVS_TS_DEPTH_STATUS_BASE 0x00001664 951 952 #define VIVS_TS_DEPTH_SURFACE_BASE 0x00001668 953 954 #define VIVS_TS_DEPTH_CLEAR_VALUE 0x0000166c 955 956 #define VIVS_TS_DEPTH_AUTO_DISABLE_COUNT 0x00001670 957 958 #define VIVS_TS_COLOR_AUTO_DISABLE_COUNT 0x00001674 959 960 #define VIVS_TS_HDEPTH_STATUS_BASE 0x000016a4 961 962 #define VIVS_TS_HDEPTH_CLEAR_VALUE 0x000016a8 963 964 #define VIVS_TS_HDEPTH_SIZE 0x000016ac 965 966 #define VIVS_TS_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 967 #define VIVS_TS_SAMPLER__ESIZE 0x00000004 968 #define VIVS_TS_SAMPLER__LEN 0x00000008 969 970 #define VIVS_TS_SAMPLER_CONFIG(i0) (0x00001720 + 0x4*(i0)) 971 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK 0x00000003 972 #define VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT 0 973 #define VIVS_TS_SAMPLER_CONFIG_ENABLE(x) (((x) << VIVS_TS_SAMPLER_CONFIG_ENABLE__SHIFT) & VIVS_TS_SAMPLER_CONFIG_ENABLE__MASK) 974 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK 0x000000f0 975 #define VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT 4 976 #define VIVS_TS_SAMPLER_CONFIG_FORMAT(x) (((x) << VIVS_TS_SAMPLER_CONFIG_FORMAT__SHIFT) & VIVS_TS_SAMPLER_CONFIG_FORMAT__MASK) 977 978 #define VIVS_TS_SAMPLER_STATUS_BASE(i0) (0x00001740 + 0x4*(i0)) 979 980 #define VIVS_TS_SAMPLER_CLEAR_VALUE(i0) (0x00001760 + 0x4*(i0)) 981 982 #define VIVS_YUV 0x00000000 983 984 #define VIVS_YUV_UNK01678 0x00001678 985 986 #define VIVS_YUV_UNK0167C 0x0000167c 987 988 #define VIVS_YUV_UNK01680 0x00001680 989 990 #define VIVS_YUV_UNK01684 0x00001684 991 992 #define VIVS_YUV_UNK01688 0x00001688 993 994 #define VIVS_YUV_UNK0168C 0x0000168c 995 996 #define VIVS_YUV_UNK01690 0x00001690 997 998 #define VIVS_YUV_UNK01694 0x00001694 999 1000 #define VIVS_YUV_UNK01698 0x00001698 1001 1002 #define VIVS_YUV_UNK0169C 0x0000169c 1003 1004 #define VIVS_TE 0x00000000 1005 1006 #define VIVS_TE_SAMPLER(i0) (0x00000000 + 0x4*(i0)) 1007 #define VIVS_TE_SAMPLER__ESIZE 0x00000004 1008 #define VIVS_TE_SAMPLER__LEN 0x0000000c 1009 1010 #define VIVS_TE_SAMPLER_CONFIG0(i0) (0x00002000 + 0x4*(i0)) 1011 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 1012 #define VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT 0 1013 #define VIVS_TE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_TYPE__MASK) 1014 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 1015 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 1016 #define VIVS_TE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_UWRAP__MASK) 1017 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 1018 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 1019 #define VIVS_TE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_VWRAP__MASK) 1020 #define VIVS_TE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 1021 #define VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT 7 1022 #define VIVS_TE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIN__MASK) 1023 #define VIVS_TE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 1024 #define VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT 9 1025 #define VIVS_TE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MIP__MASK) 1026 #define VIVS_TE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 1027 #define VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT 11 1028 #define VIVS_TE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_MAG__MASK) 1029 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 1030 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 1031 #define VIVS_TE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_FORMAT__MASK) 1032 #define VIVS_TE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 1033 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 1034 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 1035 #define VIVS_TE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ENDIAN__MASK) 1036 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 1037 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 1038 #define VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_TE_SAMPLER_CONFIG0_ANISOTROPY__MASK) 1039 1040 #define VIVS_TE_SAMPLER_SIZE(i0) (0x00002040 + 0x4*(i0)) 1041 #define VIVS_TE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff 1042 #define VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT 0 1043 #define VIVS_TE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_SIZE_WIDTH__MASK) 1044 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 1045 #define VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT 16 1046 #define VIVS_TE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_SIZE_HEIGHT__MASK) 1047 1048 #define VIVS_TE_SAMPLER_LOG_SIZE(i0) (0x00002080 + 0x4*(i0)) 1049 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff 1050 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 1051 #define VIVS_TE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_WIDTH__MASK) 1052 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 1053 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 1054 #define VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_TE_SAMPLER_LOG_SIZE_HEIGHT__MASK) 1055 1056 #define VIVS_TE_SAMPLER_LOD_CONFIG(i0) (0x000020c0 + 0x4*(i0)) 1057 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 1058 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe 1059 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 1060 #define VIVS_TE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MAX__MASK) 1061 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 1062 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 1063 #define VIVS_TE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_MIN__MASK) 1064 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 1065 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 1066 #define VIVS_TE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_TE_SAMPLER_LOD_CONFIG_BIAS__MASK) 1067 1068 #define VIVS_TE_SAMPLER_UNK02100(i0) (0x00002100 + 0x4*(i0)) 1069 1070 #define VIVS_TE_SAMPLER_UNK02140(i0) (0x00002140 + 0x4*(i0)) 1071 1072 #define VIVS_TE_SAMPLER_UNK02180(i0) (0x00002180 + 0x4*(i0)) 1073 1074 #define VIVS_TE_SAMPLER_CONFIG1(i0) (0x000021c0 + 0x4*(i0)) 1075 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f 1076 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 1077 #define VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) 1078 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 1079 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 1080 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) 1081 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 1082 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 1083 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) 1084 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 1085 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 1086 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) 1087 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 1088 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 1089 #define VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) 1090 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 1091 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 1092 #define VIVS_TE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_TE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_TE_SAMPLER_CONFIG1_HALIGN__MASK) 1093 1094 #define VIVS_TE_SAMPLER_UNK02200(i0) (0x00002200 + 0x4*(i0)) 1095 1096 #define VIVS_TE_SAMPLER_UNK02240(i0) (0x00002240 + 0x4*(i0)) 1097 1098 #define VIVS_TE_SAMPLER_LOD_ADDR(i0, i1) (0x00002400 + 0x4*(i0) + 0x40*(i1)) 1099 #define VIVS_TE_SAMPLER_LOD_ADDR__ESIZE 0x00000040 1100 #define VIVS_TE_SAMPLER_LOD_ADDR__LEN 0x0000000e 1101 1102 #define VIVS_NTE 0x00000000 1103 1104 #define VIVS_NTE_SAMPLER(i0) (0x00010000 + 0x4*(i0)) 1105 #define VIVS_NTE_SAMPLER__ESIZE 0x00000004 1106 #define VIVS_NTE_SAMPLER__LEN 0x00000020 1107 1108 #define VIVS_NTE_SAMPLER_CONFIG0(i0) (0x00010000 + 0x4*(i0)) 1109 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK 0x00000007 1110 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT 0 1111 #define VIVS_NTE_SAMPLER_CONFIG0_TYPE(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_TYPE__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_TYPE__MASK) 1112 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK 0x00000018 1113 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT 3 1114 #define VIVS_NTE_SAMPLER_CONFIG0_UWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_UWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_UWRAP__MASK) 1115 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK 0x00000060 1116 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT 5 1117 #define VIVS_NTE_SAMPLER_CONFIG0_VWRAP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_VWRAP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_VWRAP__MASK) 1118 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK 0x00000180 1119 #define VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT 7 1120 #define VIVS_NTE_SAMPLER_CONFIG0_MIN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIN__MASK) 1121 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK 0x00000600 1122 #define VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT 9 1123 #define VIVS_NTE_SAMPLER_CONFIG0_MIP(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MIP__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MIP__MASK) 1124 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK 0x00001800 1125 #define VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT 11 1126 #define VIVS_NTE_SAMPLER_CONFIG0_MAG(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_MAG__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_MAG__MASK) 1127 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK 0x0003e000 1128 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT 13 1129 #define VIVS_NTE_SAMPLER_CONFIG0_FORMAT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_FORMAT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_FORMAT__MASK) 1130 #define VIVS_NTE_SAMPLER_CONFIG0_ROUND_UV 0x00080000 1131 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK 0x00c00000 1132 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT 22 1133 #define VIVS_NTE_SAMPLER_CONFIG0_ENDIAN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ENDIAN__MASK) 1134 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK 0xff000000 1135 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT 24 1136 #define VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY(x) (((x) << VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__SHIFT) & VIVS_NTE_SAMPLER_CONFIG0_ANISOTROPY__MASK) 1137 1138 #define VIVS_NTE_SAMPLER_SIZE(i0) (0x00010080 + 0x4*(i0)) 1139 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK 0x0000ffff 1140 #define VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT 0 1141 #define VIVS_NTE_SAMPLER_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_SIZE_WIDTH__MASK) 1142 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK 0xffff0000 1143 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT 16 1144 #define VIVS_NTE_SAMPLER_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_SIZE_HEIGHT__MASK) 1145 1146 #define VIVS_NTE_SAMPLER_LOG_SIZE(i0) (0x00010100 + 0x4*(i0)) 1147 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK 0x000003ff 1148 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT 0 1149 #define VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_WIDTH__MASK) 1150 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK 0x000ffc00 1151 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT 10 1152 #define VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT(x) (((x) << VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__SHIFT) & VIVS_NTE_SAMPLER_LOG_SIZE_HEIGHT__MASK) 1153 1154 #define VIVS_NTE_SAMPLER_LOD_CONFIG(i0) (0x00010180 + 0x4*(i0)) 1155 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS_ENABLE 0x00000001 1156 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK 0x000007fe 1157 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT 1 1158 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MAX(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MAX__MASK) 1159 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK 0x001ff800 1160 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT 11 1161 #define VIVS_NTE_SAMPLER_LOD_CONFIG_MIN(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_MIN__MASK) 1162 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK 0x7fe00000 1163 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT 21 1164 #define VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS(x) (((x) << VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__SHIFT) & VIVS_NTE_SAMPLER_LOD_CONFIG_BIAS__MASK) 1165 1166 #define VIVS_NTE_SAMPLER_UNK10200(i0) (0x00010200 + 0x4*(i0)) 1167 1168 #define VIVS_NTE_SAMPLER_UNK10280(i0) (0x00010280 + 0x4*(i0)) 1169 1170 #define VIVS_NTE_SAMPLER_UNK10300(i0) (0x00010300 + 0x4*(i0)) 1171 1172 #define VIVS_NTE_SAMPLER_CONFIG1(i0) (0x00010380 + 0x4*(i0)) 1173 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK 0x0000001f 1174 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT 0 1175 #define VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_FORMAT_EXT__MASK) 1176 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK 0x00000700 1177 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT 8 1178 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_R__MASK) 1179 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK 0x00007000 1180 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT 12 1181 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_G__MASK) 1182 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK 0x00070000 1183 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT 16 1184 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_B__MASK) 1185 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK 0x00700000 1186 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT 20 1187 #define VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_SWIZZLE_A__MASK) 1188 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK 0x1c000000 1189 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT 26 1190 #define VIVS_NTE_SAMPLER_CONFIG1_HALIGN(x) (((x) << VIVS_NTE_SAMPLER_CONFIG1_HALIGN__SHIFT) & VIVS_NTE_SAMPLER_CONFIG1_HALIGN__MASK) 1191 1192 #define VIVS_NTE_SAMPLER_UNK10400(i0) (0x00010400 + 0x4*(i0)) 1193 1194 #define VIVS_NTE_SAMPLER_UNK10480(i0) (0x00010480 + 0x4*(i0)) 1195 1196 #define VIVS_NTE_SAMPLER_ADDR(i0) (0x00010800 + 0x40*(i0)) 1197 #define VIVS_NTE_SAMPLER_ADDR__ESIZE 0x00000040 1198 #define VIVS_NTE_SAMPLER_ADDR__LEN 0x00000020 1199 1200 #define VIVS_NTE_SAMPLER_ADDR_LOD(i0, i1) (0x00010800 + 0x40*(i0) + 0x4*(i1)) 1201 #define VIVS_NTE_SAMPLER_ADDR_LOD__ESIZE 0x00000004 1202 #define VIVS_NTE_SAMPLER_ADDR_LOD__LEN 0x0000000e 1203 1204 #define VIVS_NTE_UNK12000(i0) (0x00012000 + 0x4*(i0)) 1205 #define VIVS_NTE_UNK12000__ESIZE 0x00000004 1206 #define VIVS_NTE_UNK12000__LEN 0x00000100 1207 1208 #define VIVS_NTE_UNK12400(i0) (0x00012400 + 0x4*(i0)) 1209 #define VIVS_NTE_UNK12400__ESIZE 0x00000004 1210 #define VIVS_NTE_UNK12400__LEN 0x00000100 1211 1212 #define VIVS_SH 0x00000000 1213 1214 #define VIVS_SH_UNK20000(i0) (0x00020000 + 0x4*(i0)) 1215 #define VIVS_SH_UNK20000__ESIZE 0x00000004 1216 #define VIVS_SH_UNK20000__LEN 0x00002000 1217 1218 #define VIVS_SH_INST_MEM(i0) (0x0000c000 + 0x4*(i0)) 1219 #define VIVS_SH_INST_MEM__ESIZE 0x00000004 1220 #define VIVS_SH_INST_MEM__LEN 0x00001000 1221 1222 #define VIVS_SH_UNK0C000_MIRROR(i0) (0x00008000 + 0x4*(i0)) 1223 #define VIVS_SH_UNK0C000_MIRROR__ESIZE 0x00000004 1224 #define VIVS_SH_UNK0C000_MIRROR__LEN 0x00001000 1225 1226 #define VIVS_SH_UNIFORMS(i0) (0x00030000 + 0x4*(i0)) 1227 #define VIVS_SH_UNIFORMS__ESIZE 0x00000004 1228 #define VIVS_SH_UNIFORMS__LEN 0x00000400 1229 1230 1231 #endif /* STATE_3D_XML */ 1232
