1 /* 2 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <arm_def.h> 9 #include <arm_gic.h> 10 #include <assert.h> 11 #include <console.h> 12 #include <errno.h> 13 #include <plat_arm.h> 14 #include <platform.h> 15 #include <platform_def.h> 16 #include <psci.h> 17 18 /* Allow ARM Standard platforms to override this function */ 19 #pragma weak plat_arm_psci_override_pm_ops 20 21 /* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ 22 extern plat_psci_ops_t plat_arm_psci_pm_ops; 23 24 #if ARM_RECOM_STATE_ID_ENC 25 extern unsigned int arm_pm_idle_states[]; 26 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 27 28 #if !ARM_RECOM_STATE_ID_ENC 29 /******************************************************************************* 30 * ARM standard platform handler called to check the validity of the power state 31 * parameter. 32 ******************************************************************************/ 33 int arm_validate_power_state(unsigned int power_state, 34 psci_power_state_t *req_state) 35 { 36 int pstate = psci_get_pstate_type(power_state); 37 int pwr_lvl = psci_get_pstate_pwrlvl(power_state); 38 int i; 39 40 assert(req_state); 41 42 if (pwr_lvl > PLAT_MAX_PWR_LVL) 43 return PSCI_E_INVALID_PARAMS; 44 45 /* Sanity check the requested state */ 46 if (pstate == PSTATE_TYPE_STANDBY) { 47 /* 48 * It's possible to enter standby only on power level 0 49 * Ignore any other power level. 50 */ 51 if (pwr_lvl != ARM_PWR_LVL0) 52 return PSCI_E_INVALID_PARAMS; 53 54 req_state->pwr_domain_state[ARM_PWR_LVL0] = 55 ARM_LOCAL_STATE_RET; 56 } else { 57 for (i = ARM_PWR_LVL0; i <= pwr_lvl; i++) 58 req_state->pwr_domain_state[i] = 59 ARM_LOCAL_STATE_OFF; 60 } 61 62 /* 63 * We expect the 'state id' to be zero. 64 */ 65 if (psci_get_pstate_id(power_state)) 66 return PSCI_E_INVALID_PARAMS; 67 68 return PSCI_E_SUCCESS; 69 } 70 71 #else 72 /******************************************************************************* 73 * ARM standard platform handler called to check the validity of the power 74 * state parameter. The power state parameter has to be a composite power 75 * state. 76 ******************************************************************************/ 77 int arm_validate_power_state(unsigned int power_state, 78 psci_power_state_t *req_state) 79 { 80 unsigned int state_id; 81 int i; 82 83 assert(req_state); 84 85 /* 86 * Currently we are using a linear search for finding the matching 87 * entry in the idle power state array. This can be made a binary 88 * search if the number of entries justify the additional complexity. 89 */ 90 for (i = 0; !!arm_pm_idle_states[i]; i++) { 91 if (power_state == arm_pm_idle_states[i]) 92 break; 93 } 94 95 /* Return error if entry not found in the idle state array */ 96 if (!arm_pm_idle_states[i]) 97 return PSCI_E_INVALID_PARAMS; 98 99 i = 0; 100 state_id = psci_get_pstate_id(power_state); 101 102 /* Parse the State ID and populate the state info parameter */ 103 while (state_id) { 104 req_state->pwr_domain_state[i++] = state_id & 105 ARM_LOCAL_PSTATE_MASK; 106 state_id >>= ARM_LOCAL_PSTATE_WIDTH; 107 } 108 109 return PSCI_E_SUCCESS; 110 } 111 #endif /* __ARM_RECOM_STATE_ID_ENC__ */ 112 113 /******************************************************************************* 114 * ARM standard platform handler called to check the validity of the non secure 115 * entrypoint. 116 ******************************************************************************/ 117 int arm_validate_ns_entrypoint(uintptr_t entrypoint) 118 { 119 /* 120 * Check if the non secure entrypoint lies within the non 121 * secure DRAM. 122 */ 123 if ((entrypoint >= ARM_NS_DRAM1_BASE) && (entrypoint < 124 (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) 125 return PSCI_E_SUCCESS; 126 #ifndef AARCH32 127 if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint < 128 (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) 129 return PSCI_E_SUCCESS; 130 #endif 131 132 return PSCI_E_INVALID_ADDRESS; 133 } 134 135 /****************************************************************************** 136 * Default definition on ARM standard platforms to override the plat_psci_ops. 137 *****************************************************************************/ 138 const plat_psci_ops_t *plat_arm_psci_override_pm_ops(plat_psci_ops_t *ops) 139 { 140 return ops; 141 } 142 143 /****************************************************************************** 144 * Helper function to save the platform state before a system suspend. Save the 145 * state of the system components which are not in the Always ON power domain. 146 *****************************************************************************/ 147 void arm_system_pwr_domain_save(void) 148 { 149 /* Assert system power domain is available on the platform */ 150 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 151 152 plat_arm_gic_save(); 153 154 /* 155 * All the other peripheral which are configured by ARM TF are 156 * re-initialized on resume from system suspend. Hence we 157 * don't save their state here. 158 */ 159 } 160 161 /****************************************************************************** 162 * Helper function to resume the platform from system suspend. Reinitialize 163 * the system components which are not in the Always ON power domain. 164 * TODO: Unify the platform setup when waking up from cold boot and system 165 * resume in arm_bl31_platform_setup(). 166 *****************************************************************************/ 167 void arm_system_pwr_domain_resume(void) 168 { 169 console_init(PLAT_ARM_BL31_RUN_UART_BASE, PLAT_ARM_BL31_RUN_UART_CLK_IN_HZ, 170 ARM_CONSOLE_BAUDRATE); 171 172 /* Assert system power domain is available on the platform */ 173 assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2); 174 175 plat_arm_gic_resume(); 176 177 plat_arm_security_setup(); 178 arm_configure_sys_timer(); 179 } 180 181 /******************************************************************************* 182 * Private function to program the mailbox for a cpu before it is released 183 * from reset. This function assumes that the Trusted mail box base is within 184 * the ARM_SHARED_RAM region 185 ******************************************************************************/ 186 void arm_program_trusted_mailbox(uintptr_t address) 187 { 188 uintptr_t *mailbox = (void *) PLAT_ARM_TRUSTED_MAILBOX_BASE; 189 190 *mailbox = address; 191 192 /* 193 * Ensure that the PLAT_ARM_TRUSTED_MAILBOX_BASE is within 194 * ARM_SHARED_RAM region. 195 */ 196 assert((PLAT_ARM_TRUSTED_MAILBOX_BASE >= ARM_SHARED_RAM_BASE) && 197 ((PLAT_ARM_TRUSTED_MAILBOX_BASE + sizeof(*mailbox)) <= \ 198 (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE))); 199 } 200 201 /******************************************************************************* 202 * The ARM Standard platform definition of platform porting API 203 * `plat_setup_psci_ops`. 204 ******************************************************************************/ 205 int plat_setup_psci_ops(uintptr_t sec_entrypoint, 206 const plat_psci_ops_t **psci_ops) 207 { 208 *psci_ops = plat_arm_psci_override_pm_ops(&plat_arm_psci_pm_ops); 209 210 /* Setup mailbox with entry point. */ 211 arm_program_trusted_mailbox(sec_entrypoint); 212 return 0; 213 } 214
