| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| intel_extensions.c | 39 struct brw_context *brw = brw_context(ctx); local
41 assert(brw->gen >= 4);
137 if (brw->gen >= 8)
139 else if (brw->is_haswell && can_do_pipelined_register_writes(brw->screen))
141 else if (brw->gen >= 6)
150 if (brw->is_g4x || brw->gen >= 5) {
155 if (brw->gen >= 5) {
161 if (brw->gen >= 6)
[all...] |
| brw_fs_surface_builder.h | 31 namespace brw { namespace
|
| brw_vec4_surface_builder.h | 30 namespace brw { namespace
|
| brw_vec4_tes.h | 36 namespace brw { namespace
65 } /* namespace brw */
|
| intel_buffers.c | 39 struct brw_context *const brw = brw_context(ctx); local
45 dri2InvalidateDrawable(brw->driContext->driDrawablePriv);
46 intel_prepare_render(brw);
55 struct brw_context *const brw = brw_context(ctx); local
61 dri2InvalidateDrawable(brw->driContext->driReadablePriv);
62 intel_prepare_render(brw);
|
| brw_formatquery.c | 34 struct brw_context *brw = brw_context(ctx); local
39 switch (brw->gen) {
78 assert(brw->gen < 6);
|
| brw_reset.c | 36 struct brw_context *brw = brw_context(ctx); local
46 assert(brw->hw_ctx != NULL);
52 if (brw->reset_count != 0)
55 err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
64 brw->reset_count = reset_count;
73 brw->reset_count = reset_count;
81 brw_check_for_reset(struct brw_context *brw)
88 err = drm_intel_get_reset_stats(brw->hw_ctx, &reset_count, &active,
94 _mesa_set_context_lost_dispatch(&brw->ctx);
|
| brw_vec4_gs_visitor.h | 36 namespace brw { namespace
76 } /* namespace brw */
|
| brw_conditional_render.c | 41 set_predicate_enable(struct brw_context *brw,
45 brw->predicate.state = BRW_PREDICATE_STATE_RENDER;
47 brw->predicate.state = BRW_PREDICATE_STATE_DONT_RENDER;
51 set_predicate_for_result(struct brw_context *brw,
63 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
65 brw_load_register_mem64(brw,
71 brw_load_register_mem64(brw,
90 brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT;
98 struct brw_context *brw = brw_context(ctx); local
102 if (!brw->predicate.supported
136 struct brw_context *brw = brw_context(ctx); local
[all...] |
| brw_primitive_restart.c | 82 struct brw_context *brw = brw_context(ctx); local
85 if (brw->gen >= 8 || brw->is_haswell)
135 struct brw_context *brw = brw_context(ctx); local
145 if (brw->prim_restart.in_progress) {
159 brw->prim_restart.in_progress = true;
164 brw->prim_restart.enable_cut_index = true;
167 brw->prim_restart.enable_cut_index = false;
175 brw->prim_restart.in_progress = false;
182 haswell_upload_cut_index(struct brw_context *brw)
[all...] |
| brw_vec4_cmod_propagation.cpp | 36 namespace brw { namespace
172 } /* namespace brw */
|
| brw_vec4_tcs.h | 37 namespace brw { namespace
85 } /* namespace brw */
|
| hsw_sol.c | 58 save_prim_start_values(struct brw_context *brw,
62 brw_emit_mi_flush(brw);
66 brw_store_register_mem64(brw, obj->prim_count_bo,
84 tally_prims_written(struct brw_context *brw,
89 brw_emit_mi_flush(brw);
93 brw_load_register_imm32(brw, HSW_CS_GPR(0) + 4, 0);
94 brw_load_register_mem(brw, HSW_CS_GPR(0), obj->prim_count_bo,
100 brw_load_register_mem64(brw, HSW_CS_GPR(1), obj->prim_count_bo,
105 brw_load_register_reg64(brw, GEN7_SO_NUM_PRIMS_WRITTEN(i), HSW_CS_GPR(2));
124 brw_store_register_mem32(brw, obj->prim_count_bo, HSW_CS_GPR(0)
165 struct brw_context *brw = brw_context(ctx); local
199 struct brw_context *brw = brw_context(ctx); local
230 struct brw_context *brw = brw_context(ctx); local
258 struct brw_context *brw = brw_context(ctx); local
[all...] |
| intel_tex_copy.c | 47 intel_copy_texsubimage(struct brw_context *brw,
57 if (brw->ctx._ImageTransferState)
60 intel_prepare_render(brw);
86 _mesa_unlock_texture(&brw->ctx, intelImage->base.Base.TexObject);
89 ret = intel_miptree_blit(brw,
96 _mesa_lock_texture(&brw->ctx, intelImage->base.Base.TexObject);
110 struct brw_context *brw = brw_context(ctx); local
113 if (brw_blorp_copytexsubimage(brw, rb, texImage, slice, x, y,
118 if (intel_copy_texsubimage(brw,
|
| brw_ir_allocator.h | 30 namespace brw { namespace
|
| brw_vec4_gs_nir.cpp | 26 namespace brw { namespace
|
| brw_vec4_vs_visitor.cpp | 28 namespace brw { namespace
221 } /* namespace brw */
|
| brw_vs.h | 55 brw_vs_outputs_written(struct brw_context *brw, struct brw_vs_prog_key *key,
59 brw_upload_vs_prog(struct brw_context *brw);
62 brw_vs_populate_key(struct brw_context *brw,
69 namespace brw { namespace
106 } /* namespace brw */
|
| gen6_gs_visitor.h | 33 namespace brw { namespace
87 } /* namespace brw */
|
| intel_pixel_copy.c | 52 struct brw_context *brw = brw_context(ctx); local
65 intel_prepare_render(brw);
149 intel_batchbuffer_flush(brw);
173 if (!intel_miptree_blit(brw,
|
| intel_pixel_draw.c | 57 struct brw_context *brw = brw_context(ctx); local
72 intel_prepare_render(brw);
111 src_buffer = intel_bufferobj_buffer(brw, src, src_offset,
115 intel_miptree_create_for_bo(brw,
125 if (!intel_miptree_blit(brw,
154 struct brw_context *brw = brw_context(ctx); local
|
| intel_pixel_read.c | 74 struct brw_context *brw = brw_context(ctx); local
96 if (!brw->has_llc ||
141 intel_miptree_all_slices_resolve_color(brw, irb->mt, 0);
145 if (drm_intel_bo_references(brw->batch.bo, bo)) {
147 intel_batchbuffer_flush(brw);
150 error = brw_bo_map(brw, bo, false /* write enable */, "miptree");
193 brw->has_swizzling,
210 struct brw_context *brw = brw_context(ctx); local
238 brw_emit_mi_flush(brw);
247 dirty = brw->front_buffer_dirty
[all...] |
| intel_tex_subimage.c | 82 struct brw_context *brw = brw_context(ctx); local
103 if (!brw->has_llc ||
142 intel_miptree_all_slices_resolve_color(brw, image->mt, 0);
146 if (drm_intel_bo_references(brw->batch.bo, bo)) {
148 intel_batchbuffer_flush(brw);
151 error = brw_bo_map(brw, bo, true /* write enable */, "miptree");
183 brw->has_swizzling,
|
| brw_clear.c | 104 struct brw_context *brw = brw_context(ctx); local
111 if (brw->gen < 6)
156 if (brw->gen == 6 &&
163 if (brw->gen >= 8)
174 intel_miptree_all_slices_resolve_depth(brw, mt);
178 if (brw->gen == 6) {
186 brw_emit_pipe_control_flush(brw,
190 } else if (brw->gen >= 7) {
212 brw_emit_pipe_control_flush(brw,
216 brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL)
259 struct brw_context *brw = brw_context(ctx); local
[all...] |
| brw_vec4_live_variables.h | 31 namespace brw { namespace
112 } /* namespace brw */
|
