1 /* 2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__ 8 #define __SOC_ROCKCHIP_RK3399_DRAM_H__ 9 10 #include <dram_regs.h> 11 #include <plat_private.h> 12 #include <stdint.h> 13 14 enum { 15 DDR3 = 3, 16 LPDDR2 = 5, 17 LPDDR3 = 6, 18 LPDDR4 = 7, 19 UNUSED = 0xff 20 }; 21 22 struct rk3399_ddr_pctl_regs { 23 uint32_t denali_ctl[CTL_REG_NUM]; 24 }; 25 26 struct rk3399_ddr_publ_regs { 27 /* 28 * PHY registers from 0 to 90 for slice1. 29 * These are used to restore slice1-4 on resume. 30 */ 31 uint32_t phy0[91]; 32 /* 33 * PHY registers from 512 to 895. 34 * Only registers 0-37 of each 128 register range are used. 35 */ 36 uint32_t phy512[3][38]; 37 uint32_t phy896[63]; 38 }; 39 40 struct rk3399_ddr_pi_regs { 41 uint32_t denali_pi[PI_REG_NUM]; 42 }; 43 union noc_ddrtiminga0 { 44 uint32_t d32; 45 struct { 46 unsigned acttoact : 6; 47 unsigned reserved0 : 2; 48 unsigned rdtomiss : 6; 49 unsigned reserved1 : 2; 50 unsigned wrtomiss : 6; 51 unsigned reserved2 : 2; 52 unsigned readlatency : 8; 53 } b; 54 }; 55 56 union noc_ddrtimingb0 { 57 uint32_t d32; 58 struct { 59 unsigned rdtowr : 5; 60 unsigned reserved0 : 3; 61 unsigned wrtord : 5; 62 unsigned reserved1 : 3; 63 unsigned rrd : 4; 64 unsigned reserved2 : 4; 65 unsigned faw : 6; 66 unsigned reserved3 : 2; 67 } b; 68 }; 69 70 union noc_ddrtimingc0 { 71 uint32_t d32; 72 struct { 73 unsigned burstpenalty : 4; 74 unsigned reserved0 : 4; 75 unsigned wrtomwr : 6; 76 unsigned reserved1 : 18; 77 } b; 78 }; 79 80 union noc_devtodev0 { 81 uint32_t d32; 82 struct { 83 unsigned busrdtord : 3; 84 unsigned reserved0 : 1; 85 unsigned busrdtowr : 3; 86 unsigned reserved1 : 1; 87 unsigned buswrtord : 3; 88 unsigned reserved2 : 1; 89 unsigned buswrtowr : 3; 90 unsigned reserved3 : 17; 91 } b; 92 }; 93 94 union noc_ddrmode { 95 uint32_t d32; 96 struct { 97 unsigned autoprecharge : 1; 98 unsigned bypassfiltering : 1; 99 unsigned fawbank : 1; 100 unsigned burstsize : 2; 101 unsigned mwrsize : 2; 102 unsigned reserved2 : 1; 103 unsigned forceorder : 8; 104 unsigned forceorderstate : 8; 105 unsigned reserved3 : 8; 106 } b; 107 }; 108 109 struct rk3399_msch_timings { 110 union noc_ddrtiminga0 ddrtiminga0; 111 union noc_ddrtimingb0 ddrtimingb0; 112 union noc_ddrtimingc0 ddrtimingc0; 113 union noc_devtodev0 devtodev0; 114 union noc_ddrmode ddrmode; 115 uint32_t agingx0; 116 }; 117 118 struct rk3399_sdram_channel { 119 unsigned char rank; 120 /* col = 0, means this channel is invalid */ 121 unsigned char col; 122 /* 3:8bank, 2:4bank */ 123 unsigned char bk; 124 /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */ 125 unsigned char bw; 126 /* die buswidth, 2:32bit, 1:16bit, 0:8bit */ 127 unsigned char dbw; 128 /* row_3_4 = 1: 6Gb or 12Gb die 129 * row_3_4 = 0: normal die, power of 2 130 */ 131 unsigned char row_3_4; 132 unsigned char cs0_row; 133 unsigned char cs1_row; 134 uint32_t ddrconfig; 135 struct rk3399_msch_timings noc_timings; 136 }; 137 138 struct rk3399_sdram_params { 139 struct rk3399_sdram_channel ch[2]; 140 uint32_t ddr_freq; 141 unsigned char dramtype; 142 unsigned char num_channels; 143 unsigned char stride; 144 unsigned char odt; 145 struct rk3399_ddr_pctl_regs pctl_regs; 146 struct rk3399_ddr_pi_regs pi_regs; 147 struct rk3399_ddr_publ_regs phy_regs; 148 uint32_t rx_cal_dqs[2][4]; 149 }; 150 151 extern __sramdata struct rk3399_sdram_params sdram_config; 152 153 void dram_init(void); 154 155 #endif 156
