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      1 /*
      2  * Copyright (C) 2016 The Android Open Source Project
      3  *
      4  * Licensed under the Apache License, Version 2.0 (the "License");
      5  * you may not use this file except in compliance with the License.
      6  * You may obtain a copy of the License at
      7  *
      8  *      http://www.apache.org/licenses/LICENSE-2.0
      9  *
     10  * Unless required by applicable law or agreed to in writing, software
     11  * distributed under the License is distributed on an "AS IS" BASIS,
     12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13  * See the License for the specific language governing permissions and
     14  * limitations under the License.
     15  */
     16 
     17 #ifndef __PLAT_SPI_H
     18 #define __PLAT_SPI_H
     19 
     20 #include <gpio.h>
     21 #include <platform.h>
     22 #include <plat/cmsis.h>
     23 #include <plat/gpio.h>
     24 #include <plat/plat.h>
     25 
     26 struct StmSpiDmaCfg {
     27     uint8_t channel;
     28     uint8_t stream;
     29 };
     30 
     31 struct StmSpiBoardCfg {
     32     uint8_t gpioMiso;
     33     uint8_t gpioMosi;
     34     uint8_t gpioSclk;
     35     uint8_t gpioNss;
     36 
     37     enum StmGpioAltFunc gpioFunc;
     38     enum StmGpioSpeed gpioSpeed;
     39     enum GpioPullMode gpioPull;
     40 
     41     IRQn_Type irqNss;
     42 
     43     struct StmSpiDmaCfg dmaRx;
     44     struct StmSpiDmaCfg dmaTx;
     45 
     46     enum PlatSleepDevID sleepDev;
     47 };
     48 
     49 #define SPI1_DMA_BUS        1
     50 #define SPI1_DMA_RX_CFG_A   { .channel = 3, .stream = 0 }
     51 #define SPI1_DMA_RX_CFG_B   { .channel = 3, .stream = 2 }
     52 #define SPI1_DMA_TX_CFG_A   { .channel = 3, .stream = 3 }
     53 #define SPI1_DMA_TX_CFG_B   { .channel = 3, .stream = 5 }
     54 
     55 #define SPI2_DMA_BUS        0
     56 #define SPI2_DMA_RX_CFG     { .channel = 0, .stream = 3 }
     57 #define SPI2_DMA_TX_CFG     { .channel = 0, .stream = 4 }
     58 
     59 #define SPI3_DMA_BUS        0
     60 #define SPI3_DMA_RX_CFG_A   { .channel = 0, .stream = 0 }
     61 #define SPI3_DMA_RX_CFG_B   { .channel = 0, .stream = 2 }
     62 #define SPI3_DMA_TX_CFG_A   { .channel = 0, .stream = 5 }
     63 #define SPI3_DMA_TX_CFG_B   { .channel = 0, .stream = 7 }
     64 
     65 #define SPI4_DMA_BUS        1
     66 #define SPI4_DMA_RX_CFG_A   { .channel = 4, .stream = 0 }
     67 #define SPI4_DMA_RX_CFG_B   { .channel = 5, .stream = 3 }
     68 #define SPI4_DMA_TX_CFG_A   { .channel = 4, .stream = 1 }
     69 #define SPI4_DMA_TX_CFG_B   { .channel = 5, .stream = 4 }
     70 
     71 #define SPI5_DMA_BUS        1
     72 #define SPI5_DMA_RX_CFG_A   { .channel = 2, .stream = 3 }
     73 #define SPI5_DMA_RX_CFG_B   { .channel = 7, .stream = 5 }
     74 #define SPI5_DMA_TX_CFG_A   { .channel = 2, .stream = 4 }
     75 #define SPI5_DMA_TX_CFG_B   { .channel = 7, .stream = 6 }
     76 
     77 #define SPI6_DMA_BUS        1
     78 #define SPI6_DMA_RX_CFG     { .channel = 1, .stream = 6 }
     79 #define SPI6_DMA_TX_CFG     { .channel = 1, .stream = 5 }
     80 
     81 extern const struct StmSpiBoardCfg *boardStmSpiCfg(uint8_t busId);
     82 const enum IRQn spiRxIrq(uint8_t busId);
     83 const enum IRQn spiTxIrq(uint8_t busId);
     84 
     85 #endif /* __PLAT_SPI_H */
     86