1 2 #ifndef NVE4_COMPUTE_H 3 #define NVE4_COMPUTE_H 4 5 #include "nvc0/nve4_compute.xml.h" 6 7 struct nve4_cp_launch_desc 8 { 9 u32 unk0[8]; 10 u32 entry; 11 u32 unk9[2]; 12 u32 unk11_0 : 30; 13 u32 linked_tsc : 1; 14 u32 unk11_31 : 1; 15 u32 griddim_x : 31; 16 u32 unk12 : 1; 17 u16 griddim_y; 18 u16 griddim_z; 19 u32 unk14[3]; 20 u16 shared_size; /* must be aligned to 0x100 */ 21 u16 unk15; 22 u16 unk16; 23 u16 blockdim_x; 24 u16 blockdim_y; 25 u16 blockdim_z; 26 u32 cb_mask : 8; 27 u32 unk20_8 : 21; 28 u32 cache_split : 2; 29 u32 unk20_31 : 1; 30 u32 unk21[8]; 31 struct { 32 u32 address_l; 33 u32 address_h : 8; 34 u32 reserved : 7; 35 u32 size : 17; 36 } cb[8]; 37 u32 local_size_p : 20; 38 u32 unk45_20 : 7; 39 u32 bar_alloc : 5; 40 u32 local_size_n : 20; 41 u32 unk46_20 : 4; 42 u32 gpr_alloc : 8; 43 u32 cstack_size : 20; 44 u32 unk47_20 : 12; 45 u32 unk48[16]; 46 }; 47 48 static inline void 49 nve4_cp_launch_desc_init_default(struct nve4_cp_launch_desc *desc) 50 { 51 memset(desc, 0, sizeof(*desc)); 52 53 desc->unk0[7] = 0xbc000000; 54 desc->unk11_0 = 0x04014000; 55 desc->unk47_20 = 0x300; 56 } 57 58 static inline void 59 nve4_cp_launch_desc_set_cb(struct nve4_cp_launch_desc *desc, 60 unsigned index, 61 struct nouveau_bo *bo, 62 uint32_t base, uint32_t size) 63 { 64 uint64_t address = bo->offset + base; 65 66 assert(index < 8); 67 assert(!(base & 0xff)); 68 69 desc->cb[index].address_l = address; 70 desc->cb[index].address_h = address >> 32; 71 desc->cb[index].size = size; 72 73 desc->cb_mask |= 1 << index; 74 } 75 76 struct nve4_mp_trap_info { 77 u32 lock; 78 u32 pc; 79 u32 trapstat; 80 u32 warperr; 81 u32 tid[3]; 82 u32 ctaid[3]; 83 u32 pad028[2]; 84 u32 r[64]; 85 u32 flags; 86 u32 pad134[3]; 87 u32 s[0x3000]; 88 }; 89 90 #endif /* NVE4_COMPUTE_H */ 91
