| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/MarvellYukonDxe/ |
| e1000phy.c | 112 struct mii_data *mii,
152 ma.mii_data = mii;
360 struct mii_data *mii = sc->mii_pdata;
local
362 if (sc->mii_media_active != mii->mii_media_active ||
363 sc->mii_media_status != mii->mii_media_status ||
367 sc->mii_media_active = mii->mii_media_active;
368 sc->mii_media_status = mii->mii_media_status;
385 struct mii_data *mii;
local
387 mii = sc_phy->mii_sc.mii_pdata;
389 mii->mii_media_status = 0;
457 struct mii_data *mii; local
[all...] |
| if_msk.c | 309 struct mii_data *mii;
local
316 mii = &sc_if->mii_d;
319 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == (IFM_AVALID | IFM_ACTIVE)) {
322 switch (IFM_SUBTYPE (mii->mii_media_active)) {
346 // Because mii(4) notify msk (4) that it detected link status
351 switch (IFM_SUBTYPE (mii->mii_media_active)) {
364 if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG0) == 0) {
368 if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FLAG1) == 0) {
371 if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
381 if ((IFM_OPTIONS (mii->mii_media_active) & IFM_FDX) != 0) {
[all...] |
| /external/wpa_supplicant_8/src/drivers/ |
| driver_roboswitch.c | 13 #include <linux/mii.h>
22 /* MII access registers */
23 #define ROBO_MII_PAGE 0x10 /* MII page register */
24 #define ROBO_MII_ADDR 0x11 /* MII address register */
25 #define ROBO_MII_DATA_OFFSET 0x18 /* Start of MII data registers */
27 #define ROBO_MII_PAGE_ENABLE 0x01 /* MII page op code */
28 #define ROBO_MII_ADDR_WRITE 0x01 /* MII address write op code */
29 #define ROBO_MII_ADDR_READ 0x02 /* MII address read op code */
30 #define ROBO_MII_DATA_MAX 4 /* Consecutive MII data registers */
66 /* Copied from the kernel-only part of mii.h. *
88 struct mii_ioctl_data *mii = if_mii(&drv->ifr); local
105 struct mii_ioctl_data *mii = if_mii(&drv->ifr); local
[all...] |
| /external/syslinux/gpxe/src/drivers/net/ |
| sis900.c | 106 {"SiS 900 Internal MII PHY", 0x001d, 0x8000, sis900_read_mode},
123 } mii;
384 /* 630ET : set the mii access mode as software-mode */
390 /* probe for mii transceiver */
391 /* search for total of 32 possible mii phy addresses */
400 /* the mii is not accessable, try next one */
406 /* search our mii table for the current mii */
415 mii.chip_info = &mii_chip_table[i];
416 mii.phy_addr = phy_addr
122 } mii; variable in typeref:struct:mii_phy
[all...] |
| pcnet32.c | 48 #include "mii.h"
117 PCNET32_PORT_MII, /* 9 MII 10baseT */
118 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
119 PCNET32_PORT_MII, /* 11 MII (autosel) */
121 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
122 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
245 mii:1; /* mii port available */ member in struct:pcnet32_private
457 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
663 int fdx, mii, fset, dxsuflo, ltint local
[all...] |
| atl1e.h | 28 #include <mii.h>
222 struct mii_if_info mii; /* MII interface info */ member in struct:atl1e_adapter
467 #define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
468 #define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
486 /* MII PHY Status Register */
518 #define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
[all...] |
