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    Searched defs:neon (Results 1 - 3 of 3) sorted by null

  /external/tensorflow/tensorflow/core/kernels/neon/
types.h 21 namespace neon { namespace in namespace:tensorflow
70 } // end namespace neon
depthwiseconv_float.h 19 #include "tensorflow/core/kernels/neon/types.h"
27 namespace neon { namespace in namespace:tensorflow
599 // present value reflects what's realistic on ARM 32bit NEON with 16 128-bit
722 } // end namespace neon
  /toolchain/binutils/binutils-2.27/gas/config/
tc-arm.c 434 /* This does not indicate an actual NEON instruction, only that
435 the mnemonic accepts neon-style type suffixes. */
457 unsigned isscalar : 1; /* Operand is a (Neon) scalar. */
460 /* Note: we abuse "regisimm" to mean "is Neon register" in VMOV
463 unsigned isvec : 1; /* Is a single, double or quad VFP/Neon reg. */
464 unsigned isquad : 1; /* Operand is Neon quad-precision register. */
593 If TYPE is REG_TYPE_VFD or REG_TYPE_NQ, the NEON field can point to extra
595 register alias created with .dn or .qn). Otherwise NEON should be NULL. */
602 struct neon_typed_alias * neon; member in struct:reg_entry
613 N_("VFP/Neon double precision register expected")
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