1 /* 2 * Copyright 2010 Christoph Bumiller 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 23 #include "pipe/p_context.h" 24 #include "pipe/p_state.h" 25 #include "util/u_inlines.h" 26 #include "util/u_format.h" 27 #include "translate/translate.h" 28 29 #include "nv50/nv50_context.h" 30 #include "nv50/nv50_query_hw.h" 31 #include "nv50/nv50_resource.h" 32 33 #include "nv50/nv50_3d.xml.h" 34 35 void 36 nv50_vertex_state_delete(struct pipe_context *pipe, 37 void *hwcso) 38 { 39 struct nv50_vertex_stateobj *so = hwcso; 40 41 if (so->translate) 42 so->translate->release(so->translate); 43 FREE(hwcso); 44 } 45 46 void * 47 nv50_vertex_state_create(struct pipe_context *pipe, 48 unsigned num_elements, 49 const struct pipe_vertex_element *elements) 50 { 51 struct nv50_vertex_stateobj *so; 52 struct translate_key transkey; 53 unsigned i; 54 55 so = MALLOC(sizeof(*so) + 56 num_elements * sizeof(struct nv50_vertex_element)); 57 if (!so) 58 return NULL; 59 so->num_elements = num_elements; 60 so->instance_elts = 0; 61 so->instance_bufs = 0; 62 so->need_conversion = false; 63 64 memset(so->vb_access_size, 0, sizeof(so->vb_access_size)); 65 66 for (i = 0; i < PIPE_MAX_ATTRIBS; ++i) 67 so->min_instance_div[i] = 0xffffffff; 68 69 transkey.nr_elements = 0; 70 transkey.output_stride = 0; 71 72 for (i = 0; i < num_elements; ++i) { 73 const struct pipe_vertex_element *ve = &elements[i]; 74 const unsigned vbi = ve->vertex_buffer_index; 75 unsigned size; 76 enum pipe_format fmt = ve->src_format; 77 78 so->element[i].pipe = elements[i]; 79 so->element[i].state = nv50_vertex_format[fmt].vtx; 80 81 if (!so->element[i].state) { 82 switch (util_format_get_nr_components(fmt)) { 83 case 1: fmt = PIPE_FORMAT_R32_FLOAT; break; 84 case 2: fmt = PIPE_FORMAT_R32G32_FLOAT; break; 85 case 3: fmt = PIPE_FORMAT_R32G32B32_FLOAT; break; 86 case 4: fmt = PIPE_FORMAT_R32G32B32A32_FLOAT; break; 87 default: 88 assert(0); 89 FREE(so); 90 return NULL; 91 } 92 so->element[i].state = nv50_vertex_format[fmt].vtx; 93 so->need_conversion = true; 94 pipe_debug_message(&nouveau_context(pipe)->debug, FALLBACK, 95 "Converting vertex element %d, no hw format %s", 96 i, util_format_name(ve->src_format)); 97 } 98 so->element[i].state |= i; 99 100 size = util_format_get_blocksize(fmt); 101 if (so->vb_access_size[vbi] < (ve->src_offset + size)) 102 so->vb_access_size[vbi] = ve->src_offset + size; 103 104 if (1) { 105 unsigned j = transkey.nr_elements++; 106 107 transkey.element[j].type = TRANSLATE_ELEMENT_NORMAL; 108 transkey.element[j].input_format = ve->src_format; 109 transkey.element[j].input_buffer = vbi; 110 transkey.element[j].input_offset = ve->src_offset; 111 transkey.element[j].instance_divisor = ve->instance_divisor; 112 113 transkey.element[j].output_format = fmt; 114 transkey.element[j].output_offset = transkey.output_stride; 115 transkey.output_stride += (util_format_get_stride(fmt, 1) + 3) & ~3; 116 117 if (unlikely(ve->instance_divisor)) { 118 so->instance_elts |= 1 << i; 119 so->instance_bufs |= 1 << vbi; 120 if (ve->instance_divisor < so->min_instance_div[vbi]) 121 so->min_instance_div[vbi] = ve->instance_divisor; 122 } 123 } 124 } 125 126 so->translate = translate_create(&transkey); 127 so->vertex_size = transkey.output_stride / 4; 128 so->packet_vertex_limit = NV04_PFIFO_MAX_PACKET_LEN / 129 MAX2(so->vertex_size, 1); 130 131 return so; 132 } 133 134 #define NV50_3D_VERTEX_ATTRIB_INACTIVE \ 135 NV50_3D_VERTEX_ARRAY_ATTRIB_TYPE_FLOAT | \ 136 NV50_3D_VERTEX_ARRAY_ATTRIB_FORMAT_32_32_32_32 | \ 137 NV50_3D_VERTEX_ARRAY_ATTRIB_CONST 138 139 static void 140 nv50_emit_vtxattr(struct nv50_context *nv50, struct pipe_vertex_buffer *vb, 141 struct pipe_vertex_element *ve, unsigned attr) 142 { 143 struct nouveau_pushbuf *push = nv50->base.pushbuf; 144 const void *data = (const uint8_t *)vb->user_buffer + ve->src_offset; 145 float v[4]; 146 const unsigned nc = util_format_get_nr_components(ve->src_format); 147 const struct util_format_description *desc = 148 util_format_description(ve->src_format); 149 150 assert(vb->user_buffer); 151 152 if (desc->channel[0].pure_integer) { 153 if (desc->channel[0].type == UTIL_FORMAT_TYPE_SIGNED) { 154 desc->unpack_rgba_sint((int32_t *)v, 0, data, 0, 1, 1); 155 } else { 156 desc->unpack_rgba_uint((uint32_t *)v, 0, data, 0, 1, 1); 157 } 158 } else { 159 desc->unpack_rgba_float(v, 0, data, 0, 1, 1); 160 } 161 162 switch (nc) { 163 case 4: 164 BEGIN_NV04(push, NV50_3D(VTX_ATTR_4F_X(attr)), 4); 165 PUSH_DATAf(push, v[0]); 166 PUSH_DATAf(push, v[1]); 167 PUSH_DATAf(push, v[2]); 168 PUSH_DATAf(push, v[3]); 169 break; 170 case 3: 171 BEGIN_NV04(push, NV50_3D(VTX_ATTR_3F_X(attr)), 3); 172 PUSH_DATAf(push, v[0]); 173 PUSH_DATAf(push, v[1]); 174 PUSH_DATAf(push, v[2]); 175 break; 176 case 2: 177 BEGIN_NV04(push, NV50_3D(VTX_ATTR_2F_X(attr)), 2); 178 PUSH_DATAf(push, v[0]); 179 PUSH_DATAf(push, v[1]); 180 break; 181 case 1: 182 if (attr == nv50->vertprog->vp.edgeflag) { 183 BEGIN_NV04(push, NV50_3D(EDGEFLAG), 1); 184 PUSH_DATA (push, v[0] ? 1 : 0); 185 } 186 BEGIN_NV04(push, NV50_3D(VTX_ATTR_1F(attr)), 1); 187 PUSH_DATAf(push, v[0]); 188 break; 189 default: 190 assert(0); 191 break; 192 } 193 } 194 195 static inline void 196 nv50_user_vbuf_range(struct nv50_context *nv50, unsigned vbi, 197 uint32_t *base, uint32_t *size) 198 { 199 assert(vbi < PIPE_MAX_ATTRIBS); 200 if (unlikely(nv50->vertex->instance_bufs & (1 << vbi))) { 201 /* TODO: use min and max instance divisor to get a proper range */ 202 *base = 0; 203 *size = nv50->vtxbuf[vbi].buffer->width0; 204 } else { 205 /* NOTE: if there are user buffers, we *must* have index bounds */ 206 assert(nv50->vb_elt_limit != ~0); 207 *base = nv50->vb_elt_first * nv50->vtxbuf[vbi].stride; 208 *size = nv50->vb_elt_limit * nv50->vtxbuf[vbi].stride + 209 nv50->vertex->vb_access_size[vbi]; 210 } 211 } 212 213 static void 214 nv50_upload_user_buffers(struct nv50_context *nv50, 215 uint64_t addrs[], uint32_t limits[]) 216 { 217 unsigned b; 218 219 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS); 220 for (b = 0; b < nv50->num_vtxbufs; ++b) { 221 struct nouveau_bo *bo; 222 const struct pipe_vertex_buffer *vb = &nv50->vtxbuf[b]; 223 uint32_t base, size; 224 225 if (!(nv50->vbo_user & (1 << b)) || !vb->stride) 226 continue; 227 nv50_user_vbuf_range(nv50, b, &base, &size); 228 229 limits[b] = base + size - 1; 230 addrs[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, base, size, 231 &bo); 232 if (addrs[b]) 233 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, NOUVEAU_BO_GART | 234 NOUVEAU_BO_RD, bo); 235 } 236 nv50->base.vbo_dirty = true; 237 } 238 239 static void 240 nv50_update_user_vbufs(struct nv50_context *nv50) 241 { 242 uint64_t address[PIPE_MAX_ATTRIBS]; 243 struct nouveau_pushbuf *push = nv50->base.pushbuf; 244 unsigned i; 245 uint32_t written = 0; 246 247 for (i = 0; i < nv50->vertex->num_elements; ++i) { 248 struct pipe_vertex_element *ve = &nv50->vertex->element[i].pipe; 249 const unsigned b = ve->vertex_buffer_index; 250 struct pipe_vertex_buffer *vb; 251 uint32_t base, size; 252 253 assert(b < PIPE_MAX_ATTRIBS); 254 vb = &nv50->vtxbuf[b]; 255 256 if (!(nv50->vbo_user & (1 << b))) 257 continue; 258 259 if (!vb->stride) { 260 nv50_emit_vtxattr(nv50, vb, ve, i); 261 continue; 262 } 263 nv50_user_vbuf_range(nv50, b, &base, &size); 264 265 if (!(written & (1 << b))) { 266 struct nouveau_bo *bo; 267 const uint32_t bo_flags = NOUVEAU_BO_GART | NOUVEAU_BO_RD; 268 written |= 1 << b; 269 address[b] = nouveau_scratch_data(&nv50->base, vb->user_buffer, 270 base, size, &bo); 271 if (address[b]) 272 BCTX_REFN_bo(nv50->bufctx_3d, 3D_VERTEX_TMP, bo_flags, bo); 273 } 274 275 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 276 PUSH_DATAh(push, address[b] + base + size - 1); 277 PUSH_DATA (push, address[b] + base + size - 1); 278 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_START_HIGH(i)), 2); 279 PUSH_DATAh(push, address[b] + ve->src_offset); 280 PUSH_DATA (push, address[b] + ve->src_offset); 281 } 282 nv50->base.vbo_dirty = true; 283 } 284 285 static inline void 286 nv50_release_user_vbufs(struct nv50_context *nv50) 287 { 288 if (nv50->vbo_user) { 289 nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_3D_VERTEX_TMP); 290 nouveau_scratch_done(&nv50->base); 291 } 292 } 293 294 void 295 nv50_vertex_arrays_validate(struct nv50_context *nv50) 296 { 297 uint64_t addrs[PIPE_MAX_ATTRIBS]; 298 uint32_t limits[PIPE_MAX_ATTRIBS]; 299 struct nouveau_pushbuf *push = nv50->base.pushbuf; 300 struct nv50_vertex_stateobj *vertex = nv50->vertex; 301 struct pipe_vertex_buffer *vb; 302 struct nv50_vertex_element *ve; 303 uint32_t mask; 304 uint32_t refd = 0; 305 unsigned i; 306 const unsigned n = MAX2(vertex->num_elements, nv50->state.num_vtxelts); 307 308 if (unlikely(vertex->need_conversion)) 309 nv50->vbo_fifo = ~0; 310 else 311 if (nv50->vbo_user & ~nv50->vbo_constant) 312 nv50->vbo_fifo = nv50->vbo_push_hint ? ~0 : 0; 313 else 314 nv50->vbo_fifo = 0; 315 316 if (!nv50->vbo_fifo) { 317 /* if vertex buffer was written by GPU - flush VBO cache */ 318 assert(nv50->num_vtxbufs <= PIPE_MAX_ATTRIBS); 319 for (i = 0; i < nv50->num_vtxbufs; ++i) { 320 struct nv04_resource *buf = nv04_resource(nv50->vtxbuf[i].buffer); 321 if (buf && buf->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 322 buf->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 323 nv50->base.vbo_dirty = true; 324 } 325 } 326 } 327 328 /* update vertex format state */ 329 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_ATTRIB(0)), n); 330 if (nv50->vbo_fifo) { 331 nv50->state.num_vtxelts = vertex->num_elements; 332 for (i = 0; i < vertex->num_elements; ++i) 333 PUSH_DATA (push, vertex->element[i].state); 334 for (; i < n; ++i) 335 PUSH_DATA (push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 336 for (i = 0; i < n; ++i) { 337 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 338 PUSH_DATA (push, 0); 339 } 340 return; 341 } 342 for (i = 0; i < vertex->num_elements; ++i) { 343 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 344 345 assert(b < PIPE_MAX_ATTRIBS); 346 ve = &vertex->element[i]; 347 vb = &nv50->vtxbuf[b]; 348 349 if (likely(vb->stride) || !(nv50->vbo_user & (1 << b))) 350 PUSH_DATA(push, ve->state); 351 else 352 PUSH_DATA(push, ve->state | NV50_3D_VERTEX_ARRAY_ATTRIB_CONST); 353 } 354 for (; i < n; ++i) 355 PUSH_DATA(push, NV50_3D_VERTEX_ATTRIB_INACTIVE); 356 357 /* update per-instance enables */ 358 mask = vertex->instance_elts ^ nv50->state.instance_elts; 359 while (mask) { 360 const int i = ffs(mask) - 1; 361 mask &= ~(1 << i); 362 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_PER_INSTANCE(i)), 1); 363 PUSH_DATA (push, (vertex->instance_elts >> i) & 1); 364 } 365 nv50->state.instance_elts = vertex->instance_elts; 366 367 if (nv50->vbo_user & ~nv50->vbo_constant) 368 nv50_upload_user_buffers(nv50, addrs, limits); 369 370 /* update buffers and set constant attributes */ 371 for (i = 0; i < vertex->num_elements; ++i) { 372 uint64_t address, limit; 373 const unsigned b = vertex->element[i].pipe.vertex_buffer_index; 374 375 assert(b < PIPE_MAX_ATTRIBS); 376 ve = &vertex->element[i]; 377 vb = &nv50->vtxbuf[b]; 378 379 if (unlikely(nv50->vbo_constant & (1 << b))) { 380 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 381 PUSH_DATA (push, 0); 382 nv50_emit_vtxattr(nv50, vb, &ve->pipe, i); 383 continue; 384 } else 385 if (nv50->vbo_user & (1 << b)) { 386 address = addrs[b] + ve->pipe.src_offset; 387 limit = addrs[b] + limits[b]; 388 } else 389 if (!vb->buffer) { 390 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 391 PUSH_DATA (push, 0); 392 continue; 393 } else { 394 struct nv04_resource *buf = nv04_resource(vb->buffer); 395 if (!(refd & (1 << b))) { 396 refd |= 1 << b; 397 BCTX_REFN(nv50->bufctx_3d, 3D_VERTEX, buf, RD); 398 } 399 address = buf->address + vb->buffer_offset + ve->pipe.src_offset; 400 limit = buf->address + buf->base.width0 - 1; 401 } 402 403 if (unlikely(ve->pipe.instance_divisor)) { 404 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 4); 405 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 406 PUSH_DATAh(push, address); 407 PUSH_DATA (push, address); 408 PUSH_DATA (push, ve->pipe.instance_divisor); 409 } else { 410 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 3); 411 PUSH_DATA (push, NV50_3D_VERTEX_ARRAY_FETCH_ENABLE | vb->stride); 412 PUSH_DATAh(push, address); 413 PUSH_DATA (push, address); 414 } 415 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_LIMIT_HIGH(i)), 2); 416 PUSH_DATAh(push, limit); 417 PUSH_DATA (push, limit); 418 } 419 for (; i < nv50->state.num_vtxelts; ++i) { 420 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FETCH(i)), 1); 421 PUSH_DATA (push, 0); 422 } 423 nv50->state.num_vtxelts = vertex->num_elements; 424 } 425 426 #define NV50_PRIM_GL_CASE(n) \ 427 case PIPE_PRIM_##n: return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_##n 428 429 static inline unsigned 430 nv50_prim_gl(unsigned prim) 431 { 432 switch (prim) { 433 NV50_PRIM_GL_CASE(POINTS); 434 NV50_PRIM_GL_CASE(LINES); 435 NV50_PRIM_GL_CASE(LINE_LOOP); 436 NV50_PRIM_GL_CASE(LINE_STRIP); 437 NV50_PRIM_GL_CASE(TRIANGLES); 438 NV50_PRIM_GL_CASE(TRIANGLE_STRIP); 439 NV50_PRIM_GL_CASE(TRIANGLE_FAN); 440 NV50_PRIM_GL_CASE(QUADS); 441 NV50_PRIM_GL_CASE(QUAD_STRIP); 442 NV50_PRIM_GL_CASE(POLYGON); 443 NV50_PRIM_GL_CASE(LINES_ADJACENCY); 444 NV50_PRIM_GL_CASE(LINE_STRIP_ADJACENCY); 445 NV50_PRIM_GL_CASE(TRIANGLES_ADJACENCY); 446 NV50_PRIM_GL_CASE(TRIANGLE_STRIP_ADJACENCY); 447 default: 448 return NV50_3D_VERTEX_BEGIN_GL_PRIMITIVE_POINTS; 449 break; 450 } 451 } 452 453 /* For pre-nva0 transform feedback. */ 454 static const uint8_t nv50_pipe_prim_to_prim_size[PIPE_PRIM_MAX + 1] = 455 { 456 [PIPE_PRIM_POINTS] = 1, 457 [PIPE_PRIM_LINES] = 2, 458 [PIPE_PRIM_LINE_LOOP] = 2, 459 [PIPE_PRIM_LINE_STRIP] = 2, 460 [PIPE_PRIM_TRIANGLES] = 3, 461 [PIPE_PRIM_TRIANGLE_STRIP] = 3, 462 [PIPE_PRIM_TRIANGLE_FAN] = 3, 463 [PIPE_PRIM_QUADS] = 3, 464 [PIPE_PRIM_QUAD_STRIP] = 3, 465 [PIPE_PRIM_POLYGON] = 3, 466 [PIPE_PRIM_LINES_ADJACENCY] = 2, 467 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = 2, 468 [PIPE_PRIM_TRIANGLES_ADJACENCY] = 3, 469 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = 3 470 }; 471 472 static void 473 nv50_draw_arrays(struct nv50_context *nv50, 474 unsigned mode, unsigned start, unsigned count, 475 unsigned instance_count) 476 { 477 struct nouveau_pushbuf *push = nv50->base.pushbuf; 478 unsigned prim; 479 480 if (nv50->state.index_bias) { 481 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 482 PUSH_DATA (push, 0); 483 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) { 484 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1); 485 PUSH_DATA (push, 0); 486 } 487 nv50->state.index_bias = 0; 488 } 489 490 prim = nv50_prim_gl(mode); 491 492 while (instance_count--) { 493 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 494 PUSH_DATA (push, prim); 495 BEGIN_NV04(push, NV50_3D(VERTEX_BUFFER_FIRST), 2); 496 PUSH_DATA (push, start); 497 PUSH_DATA (push, count); 498 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 499 PUSH_DATA (push, 0); 500 501 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 502 } 503 } 504 505 static void 506 nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map, 507 unsigned start, unsigned count) 508 { 509 map += start; 510 511 if (count & 3) { 512 unsigned i; 513 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), count & 3); 514 for (i = 0; i < (count & 3); ++i) 515 PUSH_DATA(push, *map++); 516 count &= ~3; 517 } 518 while (count) { 519 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 4) / 4; 520 521 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U8), nr); 522 for (i = 0; i < nr; ++i) { 523 PUSH_DATA(push, 524 (map[3] << 24) | (map[2] << 16) | (map[1] << 8) | map[0]); 525 map += 4; 526 } 527 count -= nr * 4; 528 } 529 } 530 531 static void 532 nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t *map, 533 unsigned start, unsigned count) 534 { 535 map += start; 536 537 if (count & 1) { 538 count &= ~1; 539 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 540 PUSH_DATA (push, *map++); 541 } 542 while (count) { 543 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 544 545 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 546 for (i = 0; i < nr; ++i) { 547 PUSH_DATA(push, (map[1] << 16) | map[0]); 548 map += 2; 549 } 550 count -= nr * 2; 551 } 552 } 553 554 static void 555 nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t *map, 556 unsigned start, unsigned count) 557 { 558 map += start; 559 560 while (count) { 561 const unsigned nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN); 562 563 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U32), nr); 564 PUSH_DATAp(push, map, nr); 565 566 map += nr; 567 count -= nr; 568 } 569 } 570 571 static void 572 nv50_draw_elements_inline_u32_short(struct nouveau_pushbuf *push, 573 const uint32_t *map, 574 unsigned start, unsigned count) 575 { 576 map += start; 577 578 if (count & 1) { 579 count--; 580 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U32), 1); 581 PUSH_DATA (push, *map++); 582 } 583 while (count) { 584 unsigned i, nr = MIN2(count, NV04_PFIFO_MAX_PACKET_LEN * 2) / 2; 585 586 BEGIN_NI04(push, NV50_3D(VB_ELEMENT_U16), nr); 587 for (i = 0; i < nr; ++i) { 588 PUSH_DATA(push, (map[1] << 16) | map[0]); 589 map += 2; 590 } 591 count -= nr * 2; 592 } 593 } 594 595 static void 596 nv50_draw_elements(struct nv50_context *nv50, bool shorten, 597 unsigned mode, unsigned start, unsigned count, 598 unsigned instance_count, int32_t index_bias) 599 { 600 struct nouveau_pushbuf *push = nv50->base.pushbuf; 601 unsigned prim; 602 const unsigned index_size = nv50->idxbuf.index_size; 603 604 prim = nv50_prim_gl(mode); 605 606 if (index_bias != nv50->state.index_bias) { 607 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_BASE), 1); 608 PUSH_DATA (push, index_bias); 609 if (nv50->screen->base.class_3d >= NV84_3D_CLASS) { 610 BEGIN_NV04(push, NV84_3D(VERTEX_ID_BASE), 1); 611 PUSH_DATA (push, index_bias); 612 } 613 nv50->state.index_bias = index_bias; 614 } 615 616 if (nv50->idxbuf.buffer) { 617 struct nv04_resource *buf = nv04_resource(nv50->idxbuf.buffer); 618 unsigned pb_start; 619 unsigned pb_bytes; 620 const unsigned base = (buf->offset + nv50->idxbuf.offset) & ~3; 621 622 start += ((buf->offset + nv50->idxbuf.offset) & 3) >> (index_size >> 1); 623 624 assert(nouveau_resource_mapped_by_gpu(nv50->idxbuf.buffer)); 625 626 /* This shouldn't have to be here. The going theory is that the buffer 627 * is being filled in by PGRAPH, and it's not done yet by the time it 628 * gets submitted to PFIFO, which in turn starts immediately prefetching 629 * the not-yet-written data. Ideally this wait would only happen on 630 * pushbuf submit, but it's probably not a big performance difference. 631 */ 632 if (buf->fence_wr && !nouveau_fence_signalled(buf->fence_wr)) 633 nouveau_fence_wait(buf->fence_wr, &nv50->base.debug); 634 635 while (instance_count--) { 636 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 637 PUSH_DATA (push, prim); 638 639 nouveau_pushbuf_space(push, 16, 0, 1); 640 PUSH_REFN(push, buf->bo, NOUVEAU_BO_RD | buf->domain); 641 642 switch (index_size) { 643 case 4: 644 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U32), count); 645 nouveau_pushbuf_data(push, buf->bo, base + start * 4, count * 4); 646 break; 647 case 2: 648 pb_start = (start & ~1) * 2; 649 pb_bytes = ((start + count + 1) & ~1) * 2 - pb_start; 650 651 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 652 PUSH_DATA (push, (start << 31) | count); 653 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U16), pb_bytes / 4); 654 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 655 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U16_SETUP), 1); 656 PUSH_DATA (push, 0); 657 break; 658 default: 659 assert(index_size == 1); 660 pb_start = start & ~3; 661 pb_bytes = ((start + count + 3) & ~3) - pb_start; 662 663 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 664 PUSH_DATA (push, (start << 30) | count); 665 BEGIN_NL50(push, NV50_3D(VB_ELEMENT_U8), pb_bytes / 4); 666 nouveau_pushbuf_data(push, buf->bo, base + pb_start, pb_bytes); 667 BEGIN_NV04(push, NV50_3D(VB_ELEMENT_U8_SETUP), 1); 668 PUSH_DATA (push, 0); 669 break; 670 } 671 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 672 PUSH_DATA (push, 0); 673 674 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 675 } 676 } else { 677 const void *data = nv50->idxbuf.user_buffer; 678 679 while (instance_count--) { 680 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 681 PUSH_DATA (push, prim); 682 switch (index_size) { 683 case 1: 684 nv50_draw_elements_inline_u08(push, data, start, count); 685 break; 686 case 2: 687 nv50_draw_elements_inline_u16(push, data, start, count); 688 break; 689 case 4: 690 if (shorten) 691 nv50_draw_elements_inline_u32_short(push, data, start, count); 692 else 693 nv50_draw_elements_inline_u32(push, data, start, count); 694 break; 695 default: 696 assert(0); 697 return; 698 } 699 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 700 PUSH_DATA (push, 0); 701 702 prim |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 703 } 704 } 705 NOUVEAU_DRV_STAT(&nv50->screen->base, draw_calls_indexed, 1); 706 } 707 708 static void 709 nva0_draw_stream_output(struct nv50_context *nv50, 710 const struct pipe_draw_info *info) 711 { 712 struct nouveau_pushbuf *push = nv50->base.pushbuf; 713 struct nv50_so_target *so = nv50_so_target(info->count_from_stream_output); 714 struct nv04_resource *res = nv04_resource(so->pipe.buffer); 715 unsigned num_instances = info->instance_count; 716 unsigned mode = nv50_prim_gl(info->mode); 717 718 if (unlikely(nv50->screen->base.class_3d < NVA0_3D_CLASS)) { 719 /* A proper implementation without waiting doesn't seem possible, 720 * so don't bother. 721 */ 722 NOUVEAU_ERR("draw_stream_output not supported on pre-NVA0 cards\n"); 723 return; 724 } 725 726 if (res->status & NOUVEAU_BUFFER_STATUS_GPU_WRITING) { 727 res->status &= ~NOUVEAU_BUFFER_STATUS_GPU_WRITING; 728 PUSH_SPACE(push, 4); 729 BEGIN_NV04(push, SUBC_3D(NV50_GRAPH_SERIALIZE), 1); 730 PUSH_DATA (push, 0); 731 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 732 PUSH_DATA (push, 0); 733 } 734 735 assert(num_instances); 736 do { 737 PUSH_SPACE(push, 8); 738 BEGIN_NV04(push, NV50_3D(VERTEX_BEGIN_GL), 1); 739 PUSH_DATA (push, mode); 740 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_BASE), 1); 741 PUSH_DATA (push, 0); 742 BEGIN_NV04(push, NVA0_3D(DRAW_TFB_STRIDE), 1); 743 PUSH_DATA (push, so->stride); 744 nv50_hw_query_pushbuf_submit(push, NVA0_3D_DRAW_TFB_BYTES, 745 nv50_query(so->pq), 0x4); 746 BEGIN_NV04(push, NV50_3D(VERTEX_END_GL), 1); 747 PUSH_DATA (push, 0); 748 749 mode |= NV50_3D_VERTEX_BEGIN_GL_INSTANCE_NEXT; 750 } while (--num_instances); 751 } 752 753 static void 754 nv50_draw_vbo_kick_notify(struct nouveau_pushbuf *chan) 755 { 756 struct nv50_screen *screen = chan->user_priv; 757 758 nouveau_fence_update(&screen->base, true); 759 760 nv50_bufctx_fence(screen->cur_ctx->bufctx_3d, true); 761 } 762 763 void 764 nv50_draw_vbo(struct pipe_context *pipe, const struct pipe_draw_info *info) 765 { 766 struct nv50_context *nv50 = nv50_context(pipe); 767 struct nouveau_pushbuf *push = nv50->base.pushbuf; 768 bool tex_dirty = false; 769 int s; 770 771 /* NOTE: caller must ensure that (min_index + index_bias) is >= 0 */ 772 nv50->vb_elt_first = info->min_index + info->index_bias; 773 nv50->vb_elt_limit = info->max_index - info->min_index; 774 nv50->instance_off = info->start_instance; 775 nv50->instance_max = info->instance_count - 1; 776 777 /* For picking only a few vertices from a large user buffer, push is better, 778 * if index count is larger and we expect repeated vertices, suggest upload. 779 */ 780 nv50->vbo_push_hint = /* the 64 is heuristic */ 781 !(info->indexed && ((nv50->vb_elt_limit + 64) < info->count)); 782 783 if (nv50->vbo_user && !(nv50->dirty_3d & (NV50_NEW_3D_ARRAYS | NV50_NEW_3D_VERTEX))) { 784 if (!!nv50->vbo_fifo != nv50->vbo_push_hint) 785 nv50->dirty_3d |= NV50_NEW_3D_ARRAYS; 786 else 787 if (!nv50->vbo_fifo) 788 nv50_update_user_vbufs(nv50); 789 } 790 791 if (unlikely(nv50->num_so_targets && !nv50->gmtyprog)) 792 nv50->state.prim_size = nv50_pipe_prim_to_prim_size[info->mode]; 793 794 nv50_state_validate_3d(nv50, ~0); 795 796 push->kick_notify = nv50_draw_vbo_kick_notify; 797 798 for (s = 0; s < 3 && !nv50->cb_dirty; ++s) { 799 if (nv50->constbuf_coherent[s]) 800 nv50->cb_dirty = true; 801 } 802 803 /* If there are any coherent constbufs, flush the cache */ 804 if (nv50->cb_dirty) { 805 BEGIN_NV04(push, NV50_3D(CODE_CB_FLUSH), 1); 806 PUSH_DATA (push, 0); 807 nv50->cb_dirty = false; 808 } 809 810 for (s = 0; s < 3 && !tex_dirty; ++s) { 811 if (nv50->textures_coherent[s]) 812 tex_dirty = true; 813 } 814 815 if (tex_dirty) { 816 BEGIN_NV04(push, NV50_3D(TEX_CACHE_CTL), 1); 817 PUSH_DATA (push, 0x20); 818 } 819 820 if (nv50->screen->base.class_3d >= NVA0_3D_CLASS && 821 nv50->seamless_cube_map != nv50->state.seamless_cube_map) { 822 nv50->state.seamless_cube_map = nv50->seamless_cube_map; 823 BEGIN_NV04(push, SUBC_3D(NVA0_3D_TEX_MISC), 1); 824 PUSH_DATA (push, nv50->seamless_cube_map ? NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0); 825 } 826 827 if (nv50->vbo_fifo) { 828 nv50_push_vbo(nv50, info); 829 push->kick_notify = nv50_default_kick_notify; 830 nouveau_pushbuf_bufctx(push, NULL); 831 return; 832 } 833 834 if (nv50->state.instance_base != info->start_instance) { 835 nv50->state.instance_base = info->start_instance; 836 /* NOTE: this does not affect the shader input, should it ? */ 837 BEGIN_NV04(push, NV50_3D(VB_INSTANCE_BASE), 1); 838 PUSH_DATA (push, info->start_instance); 839 } 840 841 nv50->base.vbo_dirty |= !!nv50->vtxbufs_coherent; 842 843 if (nv50->base.vbo_dirty) { 844 BEGIN_NV04(push, NV50_3D(VERTEX_ARRAY_FLUSH), 1); 845 PUSH_DATA (push, 0); 846 nv50->base.vbo_dirty = false; 847 } 848 849 if (info->indexed) { 850 bool shorten = info->max_index <= 65535; 851 852 if (info->primitive_restart != nv50->state.prim_restart) { 853 if (info->primitive_restart) { 854 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 2); 855 PUSH_DATA (push, 1); 856 PUSH_DATA (push, info->restart_index); 857 858 if (info->restart_index > 65535) 859 shorten = false; 860 } else { 861 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_ENABLE), 1); 862 PUSH_DATA (push, 0); 863 } 864 nv50->state.prim_restart = info->primitive_restart; 865 } else 866 if (info->primitive_restart) { 867 BEGIN_NV04(push, NV50_3D(PRIM_RESTART_INDEX), 1); 868 PUSH_DATA (push, info->restart_index); 869 870 if (info->restart_index > 65535) 871 shorten = false; 872 } 873 874 nv50_draw_elements(nv50, shorten, 875 info->mode, info->start, info->count, 876 info->instance_count, info->index_bias); 877 } else 878 if (unlikely(info->count_from_stream_output)) { 879 nva0_draw_stream_output(nv50, info); 880 } else { 881 nv50_draw_arrays(nv50, 882 info->mode, info->start, info->count, 883 info->instance_count); 884 } 885 push->kick_notify = nv50_default_kick_notify; 886 887 nv50_release_user_vbufs(nv50); 888 889 nouveau_pushbuf_bufctx(push, NULL); 890 } 891
