| /art/compiler/jni/quick/ |
| jni_compiler.cc | 357 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local
358 __ CreateHandleScopeEntry(out_reg, class_handle_scope_offset,
404 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local
405 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset,
479 ManagedRegister out_reg = main_jni_conv->CurrentParamRegister(); local
480 __ CreateHandleScopeEntry(out_reg, handle_scope_offset,
599 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local
600 __ Load(out_reg, saved_cookie_offset, 4);
611 ManagedRegister out_reg = end_jni_conv->CurrentParamRegister(); local
612 __ CreateHandleScopeEntry(out_reg, locked_object_handle_scope_offset
699 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local
723 ManagedRegister out_reg = jni_conv->CurrentParamRegister(); local
[all...] |
| /art/compiler/utils/arm/ |
| jni_macro_assembler_arm_vixl.cc | 474 ArmManagedRegister out_reg = mout_reg.AsArm(); local
477 CHECK(out_reg.IsCoreRegister()) << out_reg;
479 temps.Exclude(out_reg.AsVIXLRegister());
483 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
486 out_reg.AsVIXLRegister(),
489 in_reg = out_reg;
496 if (!out_reg.Equals(in_reg)) {
501 ___ mov(eq, out_reg.AsVIXLRegister(), 0);
502 asm_.AddConstantInIt(out_reg.AsVIXLRegister(), sp, handle_scope_offset.Int32Value(), ne)
[all...] |
| /art/compiler/utils/x86/ |
| jni_macro_assembler_x86.cc | 428 X86ManagedRegister out_reg = mout_reg.AsX86(); local
431 CHECK(out_reg.IsCpuRegister());
435 if (!out_reg.Equals(in_reg)) {
436 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
440 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset));
443 __ leal(out_reg.AsCpuRegister(), Address(ESP, handle_scope_offset));
469 X86ManagedRegister out_reg = mout_reg.AsX86(); local
471 CHECK(out_reg.IsCpuRegister());
474 if (!out_reg.Equals(in_reg))
[all...] |
| /art/compiler/utils/x86_64/ |
| jni_macro_assembler_x86_64.cc | 479 X86_64ManagedRegister out_reg = mout_reg.AsX86_64(); local
482 // Use out_reg as indicator of null.
483 in_reg = out_reg;
488 CHECK(out_reg.IsCpuRegister());
492 if (!out_reg.Equals(in_reg)) {
493 __ xorl(out_reg.AsCpuRegister(), out_reg.AsCpuRegister());
497 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
500 __ leaq(out_reg.AsCpuRegister(), Address(CpuRegister(RSP), handle_scope_offset));
526 X86_64ManagedRegister out_reg = mout_reg.AsX86_64() local
[all...] |
| /art/compiler/utils/arm64/ |
| jni_macro_assembler_arm64.cc | 561 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); local
565 CHECK(out_reg.IsXRegister()) << out_reg;
569 // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset)
571 LoadWFromOffset(kLoadWord, out_reg.AsOverlappingWRegister(), SP,
573 in_reg = out_reg;
576 if (!out_reg.Equals(in_reg)) {
577 LoadImmediate(out_reg.AsXRegister(), 0, eq);
579 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), ne);
581 AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), al)
608 Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); local
[all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm64.cc | 544 FPRegister out_reg = is64bit ? DRegisterFrom(out) : SRegisterFrom(out); local
546 __ Fabs(out_reg, in_reg);
572 Register out_reg = is64bit ? XRegisterFrom(output) : WRegisterFrom(output); local
575 __ Cneg(out_reg, in_reg, lt);
604 FPRegister out_reg = is_double ? DRegisterFrom(out) : SRegisterFrom(out); local
606 __ Fmin(out_reg, op1_reg, op2_reg);
608 __ Fmax(out_reg, op1_reg, op2_reg);
663 Register out_reg = is_long ? XRegisterFrom(out) : WRegisterFrom(out); local
666 __ Csel(out_reg, op1_reg, op2_reg, is_min ? lt : gt);
766 Register out_reg = is_double ? XRegisterFrom(l->Out()) : WRegisterFrom(l->Out()) local
[all...] |
| intrinsics_arm_vixl.cc | 487 vixl32::Register out_reg = RegisterFrom(output); local
490 __ Add(out_reg, in_reg, mask);
491 __ Eor(out_reg, mask, out_reg);
806 vixl32::Register out_reg = OutputRegister(invoke); local
814 __ Vmov(out_reg, temp1);
817 __ Cmp(out_reg, 0);
822 // If input is a negative tie, change rounding direction to positive infinity, out_reg += 1.
834 __ add(eq, out_reg, out_reg, 1)
[all...] |
| code_generator_arm_vixl.cc | 4647 vixl32::Register out_reg = OutputRegister(rem); local
4931 vixl32::Register out_reg = OutputRegister(op); local
7986 vixl32::Register out_reg = RegisterFrom(out); local
8204 vixl32::Register out_reg = OutputRegister(instruction); local
8238 vixl32::Register out_reg = OutputRegister(instruction); local
8275 vixl32::Register out_reg = RegisterFrom(out); local
8289 __ Mov(RegisterFrom(maybe_temp), out_reg); local
8309 vixl32::Register out_reg = RegisterFrom(out); local
[all...] |
| code_generator_mips.cc | 6776 Register out_reg = out.AsRegister<Register>(); local
6816 Register out_reg = out.AsRegister<Register>(); local
[all...] |
| code_generator_x86.cc | 7088 Register out_reg = out.AsRegister<Register>(); local
7121 Register out_reg = out.AsRegister<Register>(); local
[all...] |
| code_generator_x86_64.cc | 6470 CpuRegister out_reg = out.AsRegister<CpuRegister>(); local
6503 CpuRegister out_reg = out.AsRegister<CpuRegister>(); local
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips.cc | 5102 MipsManagedRegister out_reg = mout_reg.AsMips(); local
5151 MipsManagedRegister out_reg = mout_reg.AsMips(); local
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.cc | 3937 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); local
3987 Mips64ManagedRegister out_reg = mout_reg.AsMips64(); local
[all...] |
| /external/valgrind/perf/ |
| tinycc.c | 17979 int nb_outputs, nb_operands, i, must_subst, out_reg; local
[all...] |
