1 /* 2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef __TEGRA_PRIVATE_H__ 8 #define __TEGRA_PRIVATE_H__ 9 10 #include <arch.h> 11 #include <platform_def.h> 12 #include <psci.h> 13 #include <xlat_tables.h> 14 15 /******************************************************************************* 16 * Tegra DRAM memory base address 17 ******************************************************************************/ 18 #define TEGRA_DRAM_BASE ULL(0x80000000) 19 #define TEGRA_DRAM_END ULL(0x27FFFFFFF) 20 21 /******************************************************************************* 22 * Struct for parameters received from BL2 23 ******************************************************************************/ 24 typedef struct plat_params_from_bl2 { 25 /* TZ memory size */ 26 uint64_t tzdram_size; 27 /* TZ memory base */ 28 uint64_t tzdram_base; 29 /* UART port ID */ 30 int uart_id; 31 } plat_params_from_bl2_t; 32 33 /******************************************************************************* 34 * Per-CPU struct describing FIQ state to be stored 35 ******************************************************************************/ 36 typedef struct pcpu_fiq_state { 37 uint64_t elr_el3; 38 uint64_t spsr_el3; 39 } pcpu_fiq_state_t; 40 41 /******************************************************************************* 42 * Struct describing per-FIQ configuration settings 43 ******************************************************************************/ 44 typedef struct irq_sec_cfg { 45 /* IRQ number */ 46 unsigned int irq; 47 /* Target CPUs servicing this interrupt */ 48 unsigned int target_cpus; 49 /* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */ 50 uint32_t type; 51 } irq_sec_cfg_t; 52 53 /* Declarations for plat_psci_handlers.c */ 54 int32_t tegra_soc_validate_power_state(unsigned int power_state, 55 psci_power_state_t *req_state); 56 57 /* Declarations for plat_setup.c */ 58 const mmap_region_t *plat_get_mmio_map(void); 59 uint32_t plat_get_console_from_id(int id); 60 void plat_gic_setup(void); 61 bl31_params_t *plat_get_bl31_params(void); 62 plat_params_from_bl2_t *plat_get_bl31_plat_params(void); 63 64 /* Declarations for plat_secondary.c */ 65 void plat_secondary_setup(void); 66 int plat_lock_cpu_vectors(void); 67 68 /* Declarations for tegra_fiq_glue.c */ 69 void tegra_fiq_handler_setup(void); 70 int tegra_fiq_get_intr_context(void); 71 void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint); 72 73 /* Declarations for tegra_gic.c */ 74 void tegra_gic_cpuif_deactivate(void); 75 void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs); 76 77 /* Declarations for tegra_security.c */ 78 void tegra_security_setup(void); 79 void tegra_security_setup_videomem(uintptr_t base, uint64_t size); 80 81 /* Declarations for tegra_pm.c */ 82 extern uint8_t tegra_fake_system_suspend; 83 84 void tegra_pm_system_suspend_entry(void); 85 void tegra_pm_system_suspend_exit(void); 86 int tegra_system_suspended(void); 87 88 /* Declarations for tegraXXX_pm.c */ 89 int tegra_prepare_cpu_suspend(unsigned int id, unsigned int afflvl); 90 int tegra_prepare_cpu_on_finish(unsigned long mpidr); 91 92 /* Declarations for tegra_bl31_setup.c */ 93 plat_params_from_bl2_t *bl31_get_plat_params(void); 94 int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); 95 void plat_early_platform_setup(void); 96 97 /* Declarations for tegra_delay_timer.c */ 98 void tegra_delay_timer_init(void); 99 100 void tegra_secure_entrypoint(void); 101 void tegra186_cpu_reset_handler(void); 102 103 #endif /* __TEGRA_PRIVATE_H__ */ 104
