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      1 /*
      2  * Copyright (c) 2013-2015, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * SPDX-License-Identifier: BSD-3-Clause
      5  */
      6 
      7 /* ZynqMP power management enums and defines */
      8 
      9 #ifndef _PM_DEFS_H_
     10 #define _PM_DEFS_H_
     11 
     12 /*********************************************************************
     13  * Macro definitions
     14  ********************************************************************/
     15 
     16 /*
     17  * Version number is a 32bit value, like:
     18  * (PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR
     19  */
     20 #define PM_VERSION_MAJOR	0
     21 #define PM_VERSION_MINOR	2
     22 
     23 #define PM_VERSION	((PM_VERSION_MAJOR << 16) | PM_VERSION_MINOR)
     24 
     25 /* Capabilities for RAM */
     26 #define PM_CAP_ACCESS	0x1U
     27 #define PM_CAP_CONTEXT	0x2U
     28 
     29 #define MAX_LATENCY	(~0U)
     30 #define MAX_QOS		100U
     31 
     32 /* State arguments of the self suspend */
     33 #define PM_STATE_CPU_IDLE		0x0U
     34 #define PM_STATE_SUSPEND_TO_RAM		0xFU
     35 
     36 /*********************************************************************
     37  * Enum definitions
     38  ********************************************************************/
     39 
     40 enum pm_api_id {
     41 	/* Miscellaneous API functions: */
     42 	PM_GET_API_VERSION = 1, /* Do not change or move */
     43 	PM_SET_CONFIGURATION,
     44 	PM_GET_NODE_STATUS,
     45 	PM_GET_OP_CHARACTERISTIC,
     46 	PM_REGISTER_NOTIFIER,
     47 	/* API for suspending of PUs: */
     48 	PM_REQ_SUSPEND,
     49 	PM_SELF_SUSPEND,
     50 	PM_FORCE_POWERDOWN,
     51 	PM_ABORT_SUSPEND,
     52 	PM_REQ_WAKEUP,
     53 	PM_SET_WAKEUP_SOURCE,
     54 	PM_SYSTEM_SHUTDOWN,
     55 	/* API for managing PM slaves: */
     56 	PM_REQ_NODE,
     57 	PM_RELEASE_NODE,
     58 	PM_SET_REQUIREMENT,
     59 	PM_SET_MAX_LATENCY,
     60 	/* Direct control API functions: */
     61 	PM_RESET_ASSERT,
     62 	PM_RESET_GET_STATUS,
     63 	PM_MMIO_WRITE,
     64 	PM_MMIO_READ,
     65 	PM_INIT,
     66 	PM_FPGA_LOAD,
     67 	PM_FPGA_GET_STATUS,
     68 	PM_GET_CHIPID,
     69 	PM_API_MAX
     70 };
     71 
     72 enum pm_node_id {
     73 	NODE_UNKNOWN = 0,
     74 	NODE_APU,
     75 	NODE_APU_0,
     76 	NODE_APU_1,
     77 	NODE_APU_2,
     78 	NODE_APU_3,
     79 	NODE_RPU,
     80 	NODE_RPU_0,
     81 	NODE_RPU_1,
     82 	NODE_PL,
     83 	NODE_FPD,
     84 	NODE_OCM_BANK_0,
     85 	NODE_OCM_BANK_1,
     86 	NODE_OCM_BANK_2,
     87 	NODE_OCM_BANK_3,
     88 	NODE_TCM_0_A,
     89 	NODE_TCM_0_B,
     90 	NODE_TCM_1_A,
     91 	NODE_TCM_1_B,
     92 	NODE_L2,
     93 	NODE_GPU_PP_0,
     94 	NODE_GPU_PP_1,
     95 	NODE_USB_0,
     96 	NODE_USB_1,
     97 	NODE_TTC_0,
     98 	NODE_TTC_1,
     99 	NODE_TTC_2,
    100 	NODE_TTC_3,
    101 	NODE_SATA,
    102 	NODE_ETH_0,
    103 	NODE_ETH_1,
    104 	NODE_ETH_2,
    105 	NODE_ETH_3,
    106 	NODE_UART_0,
    107 	NODE_UART_1,
    108 	NODE_SPI_0,
    109 	NODE_SPI_1,
    110 	NODE_I2C_0,
    111 	NODE_I2C_1,
    112 	NODE_SD_0,
    113 	NODE_SD_1,
    114 	NODE_DP,
    115 	NODE_GDMA,
    116 	NODE_ADMA,
    117 	NODE_NAND,
    118 	NODE_QSPI,
    119 	NODE_GPIO,
    120 	NODE_CAN_0,
    121 	NODE_CAN_1,
    122 	NODE_AFI,
    123 	NODE_APLL,
    124 	NODE_VPLL,
    125 	NODE_DPLL,
    126 	NODE_RPLL,
    127 	NODE_IOPLL,
    128 	NODE_DDR,
    129 	NODE_IPI_APU,
    130 	NODE_IPI_RPU_0,
    131 	NODE_GPU,
    132 	NODE_PCIE,
    133 	NODE_PCAP,
    134 	NODE_RTC,
    135 	NODE_MAX
    136 };
    137 
    138 enum pm_request_ack {
    139 	REQ_ACK_NO = 1,
    140 	REQ_ACK_BLOCKING,
    141 	REQ_ACK_NON_BLOCKING,
    142 };
    143 
    144 enum pm_abort_reason {
    145 	ABORT_REASON_WKUP_EVENT = 100,
    146 	ABORT_REASON_PU_BUSY,
    147 	ABORT_REASON_NO_PWRDN,
    148 	ABORT_REASON_UNKNOWN,
    149 };
    150 
    151 enum pm_suspend_reason {
    152 	SUSPEND_REASON_PU_REQ = 201,
    153 	SUSPEND_REASON_ALERT,
    154 	SUSPEND_REASON_SYS_SHUTDOWN,
    155 };
    156 
    157 enum pm_ram_state {
    158 	PM_RAM_STATE_OFF = 1,
    159 	PM_RAM_STATE_RETENTION,
    160 	PM_RAM_STATE_ON,
    161 };
    162 
    163 enum pm_opchar_type {
    164 	PM_OPCHAR_TYPE_POWER = 1,
    165 	PM_OPCHAR_TYPE_TEMP,
    166 	PM_OPCHAR_TYPE_LATENCY,
    167 };
    168 
    169 /**
    170  * @PM_RET_SUCCESS:		success
    171  * @PM_RET_ERROR_ARGS:		illegal arguments provided
    172  * @PM_RET_ERROR_ACCESS:	access rights violation
    173  * @PM_RET_ERROR_TIMEOUT:	timeout in communication with PMU
    174  * @PM_RET_ERROR_NOTSUPPORTED:	feature not supported
    175  * @PM_RET_ERROR_PROC:		node is not a processor node
    176  * @PM_RET_ERROR_API_ID:	illegal API ID
    177  * @PM_RET_ERROR_OTHER:		other error
    178  */
    179 enum pm_ret_status {
    180 	PM_RET_SUCCESS,
    181 	PM_RET_ERROR_ARGS,
    182 	PM_RET_ERROR_ACCESS,
    183 	PM_RET_ERROR_TIMEOUT,
    184 	PM_RET_ERROR_NOTSUPPORTED,
    185 	PM_RET_ERROR_PROC,
    186 	PM_RET_ERROR_API_ID,
    187 	PM_RET_ERROR_FAILURE,
    188 	PM_RET_ERROR_COMMUNIC,
    189 	PM_RET_ERROR_DOUBLEREQ,
    190 	PM_RET_ERROR_OTHER,
    191 };
    192 
    193 /**
    194  * @PM_INITIAL_BOOT:	boot is a fresh system startup
    195  * @PM_RESUME:		boot is a resume
    196  * @PM_BOOT_ERROR:	error, boot cause cannot be identified
    197  */
    198 enum pm_boot_status {
    199 	PM_INITIAL_BOOT,
    200 	PM_RESUME,
    201 	PM_BOOT_ERROR,
    202 };
    203 
    204 enum pm_shutdown_type {
    205 	PMF_SHUTDOWN_TYPE_SHUTDOWN,
    206 	PMF_SHUTDOWN_TYPE_RESET,
    207 };
    208 
    209 enum pm_shutdown_subtype {
    210 	PMF_SHUTDOWN_SUBTYPE_SUBSYSTEM,
    211 	PMF_SHUTDOWN_SUBTYPE_PS_ONLY,
    212 	PMF_SHUTDOWN_SUBTYPE_SYSTEM,
    213 };
    214 
    215 #endif /* _PM_DEFS_H_ */
    216