/art/runtime/interpreter/ |
shadow_frame.cc | 32 uint16_t reg = accessor.RegistersSize() - accessor.InsSize(); local 33 return GetVRegReference(reg);
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/hardware/intel/common/libmix/mix_vbp/viddec_fw/fw/parser/ |
viddec_intr.c | 22 uint32_t reg=0, temp=0; local 29 reg = reg_read(INT_STATUS); 39 //reg = reg_read(INT_STATUS); 53 //DEBUG_WRITE(0xff, timer, temp, reg, 0, val);
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/device/linaro/bootloader/arm-trusted-firmware/plat/arm/board/juno/ |
juno_security.c | 22 uint32_t reg = mmio_read_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET); local 23 reg |= 0x1FF; 24 mmio_write_32(MMU401_DMA330_BASE + MMU401_SSD_OFFSET, reg);
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/external/valgrind/coregrind/m_gdbserver/ |
regdef.h | 25 struct reg struct 45 void set_register_cache (struct reg *regs, int n);
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/art/test/404-optimizing-allocator/src/ |
Main.java | 17 // Note that $opt$reg$ is a marker for the optimizing compiler to test 23 expectEquals(4, $opt$reg$TestLostCopy()); 24 expectEquals(-10, $opt$reg$TestTwoLive()); 25 expectEquals(-20, $opt$reg$TestThreeLive()); 26 expectEquals(5, $opt$reg$TestFourLive()); 27 expectEquals(10, $opt$reg$TestMultipleLive()); 28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); 29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); 30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); 31 expectEquals(-77, $opt$reg$TestAgressiveLive2(1, 2, 3, 4, 5, 6, 7)) [all...] |
/bionic/tests/ |
sys_procfs_test.cpp | 22 elf_greg_t reg; local 23 memset(®, 0, sizeof(reg));
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/external/elfutils/libdw/ |
dwarf_frame_register.c | 56 const struct dwarf_frame_register *reg = &fs->regs[regno]; local 58 switch (reg->rule) 79 if (reg->value != 0) 81 .number = reg->value }; 82 if (reg->rule == reg_val_offset) 90 .number = reg->value }; 100 const uint8_t *p = fs->cache->data->d.d_buf + reg->value; 111 true, reg->rule == reg_val_expression,
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/external/wpa_supplicant_8/src/wps/ |
wps_upnp_ap.c | 22 struct wps_registrar *reg = timeout_ctx; local 25 wps_registrar_selected_registrar_changed(reg, 0); 29 int upnp_er_set_selected_registrar(struct wps_registrar *reg, 41 s->reg = reg; 42 eloop_cancel_timeout(upnp_er_set_selected_timeout, s, reg); 67 upnp_er_set_selected_timeout, s, reg); 70 wps_registrar_selected_registrar_changed(reg, 0); 76 void upnp_er_remove_notification(struct wps_registrar *reg, 80 eloop_cancel_timeout(upnp_er_set_selected_timeout, s, reg); [all...] |
/art/compiler/utils/x86/ |
managed_register_x86_test.cc | 26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local 27 EXPECT_TRUE(reg.IsNoRegister()); 28 EXPECT_TRUE(!reg.Overlaps(reg)); 32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local 33 EXPECT_TRUE(!reg.IsNoRegister()); 34 EXPECT_TRUE(reg.IsCpuRegister()); 35 EXPECT_TRUE(!reg.IsXmmRegister()); 36 EXPECT_TRUE(!reg.IsX87Register()); 37 EXPECT_TRUE(!reg.IsRegisterPair()) 66 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local 92 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local 118 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local 256 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local [all...] |
managed_register_x86.cc | 41 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86::RegisterPairDescriptor 53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { 54 if (reg == kNoRegisterPair) { 57 os << X86ManagedRegister::FromRegisterPair(reg); 84 CHECK_EQ(r, kRegisterPairs[r].reg); 93 CHECK_EQ(r, kRegisterPairs[r].reg); 114 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { 115 reg.Print(os);
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/art/compiler/utils/x86_64/ |
managed_register_x86_64_test.cc | 25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_TRUE(!reg.Overlaps(reg)); 31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local 32 EXPECT_TRUE(!reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsCpuRegister()); 34 EXPECT_TRUE(!reg.IsXmmRegister()); 35 EXPECT_TRUE(!reg.IsX87Register()); 36 EXPECT_TRUE(!reg.IsRegisterPair()) 65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); local 91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); local 117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); local 255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); local [all...] |
managed_register_x86_64.cc | 40 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86_64::RegisterPairDescriptor 52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { 53 os << X86_64ManagedRegister::FromRegisterPair(reg); 79 CHECK_EQ(r, kRegisterPairs[r].reg); 88 CHECK_EQ(r, kRegisterPairs[r].reg); 109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { 110 reg.Print(os);
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/device/linaro/bootloader/arm-trusted-firmware/plat/nvidia/tegra/common/drivers/pmc/ |
pmc.c | 103 uint32_t reg; local 105 reg = tegra_pmc_read_32(PMC_CONFIG); 106 reg |= RESET_ENABLE; /* restart */ 107 tegra_pmc_write_32(PMC_CONFIG, reg);
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/external/capstone/bindings/python/capstone/ |
mips.py | 16 ('reg', ctypes.c_uint), 32 def reg(self): member in class:MipsOp 33 return self.value.reg
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sparc.py | 17 ('reg', ctypes.c_uint), 33 def reg(self): member in class:SparcOp 34 return self.value.reg
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systemz.py | 18 ('reg', ctypes.c_uint), 34 def reg(self): member in class:SyszOp 35 return self.value.reg
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x86.py | 19 ('reg', ctypes.c_uint), 39 def reg(self): member in class:X86Op 40 return self.value.reg
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xcore.py | 18 ('reg', ctypes.c_uint), 34 def reg(self): member in class:XcoreOp 35 return self.value.reg
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/external/clang/test/Index/ |
get-cursor.c | 16 r_t reg; local 17 reg.field = 1;
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/external/libunwind/src/x86/ |
Gresume.c | 45 int reg; local 52 for (reg = 0; reg <= UNW_REG_LAST; ++reg) 54 Debug (16, "copying %s %d\n", unw_regname (reg), reg); 55 if (unw_is_fpreg (reg)) 57 if (tdep_access_fpreg (c, reg, &fpval, 0) >= 0) 58 (*access_fpreg) (as, reg, &fpval, 1, arg); 62 if (tdep_access_reg (c, reg, &val, 0) >= 0 [all...] |
/external/mesa3d/src/gallium/drivers/svga/ |
svga_link.c | 102 unsigned reg = 0; local 117 if (reg & 1 << linkage->input_map[i]) { 120 reg |= 1 << linkage->input_map[i];
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/external/tensorflow/tensorflow/contrib/lite/ |
optional_debug_tools.cc | 95 const TfLiteRegistration& reg = node_and_reg->second; local 97 reg.builtin_code);
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/art/compiler/utils/mips64/ |
managed_register_mips64_test.cc | 25 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_FALSE(reg.Overlaps(reg)); 31 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); local 32 EXPECT_FALSE(reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsGpuRegister()); 34 EXPECT_FALSE(reg.IsFpuRegister()); 35 EXPECT_FALSE(reg.IsVectorRegister()); 36 EXPECT_EQ(ZERO, reg.AsGpuRegister()) 110 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local 156 Mips64ManagedRegister reg = Mips64ManagedRegister::FromVectorRegister(W0); local 278 Mips64ManagedRegister reg = Mips64ManagedRegister::FromFpuRegister(F0); local [all...] |
/art/runtime/ |
check_reference_map_visitor.h | 77 int reg = registers[i]; local 78 CHECK_LT(reg, accessor.RegistersSize()); 80 reg, number_of_dex_registers, code_info, encoding);
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common_dex_operations.h | 196 ObjPtr<mirror::Object> reg = value.GetL(); local 197 if (do_assignability_check && reg != nullptr) { 203 HandleWrapperObjPtr<mirror::Object> h_reg(hs.NewHandleWrapper(®)); 207 if (!reg->VerifierInstanceOf(field_class.Ptr())) { 212 reg->GetClass()->GetDescriptor(&temp1), 218 field->SetObj<transaction_active>(obj, reg);
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