| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 920 void Assembler::rev16(const Register& rd, const Register& rn) { function in class:vixl::aarch64::Assembler
921 DataProcessing1Source(rd, rn, REV16);
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| logic-aarch64.cc | 2320 LogicVRegister Simulator::rev16(VectorFormat vform, function in class:vixl::aarch64::Simulator
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| /external/v8/src/arm64/ |
| assembler-arm64.cc | 1546 void Assembler::rev16(const Register& rd, function in class:v8::internal::Assembler
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| /external/vixl/src/aarch32/ |
| assembler-aarch32.cc | 8846 void Assembler::rev16(Condition cond, function in class:vixl::aarch32::Assembler
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| assembler-aarch32.h | 2832 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } function in class:vixl::aarch32::Assembler
2833 void rev16(Condition cond, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
2836 void rev16(EncodingSize size, Register rd, Register rm) { function in class:vixl::aarch32::Assembler
[all...] |
| disasm-aarch32.cc | 2259 void Disassembler::rev16(Condition cond, function in class:vixl::aarch32::Disassembler
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