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      1 /** @file
      2 *
      3 *  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
      4 *  Copyright (c) 2016, Linaro Limited. All rights reserved.
      5 *
      6 *  This program and the accompanying materials
      7 *  are licensed and made available under the terms and conditions of the BSD License
      8 *  which accompanies this distribution.  The full text of the license may be found at
      9 *  http://opensource.org/licenses/bsd-license.php
     10 *
     11 *  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
     12 *  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
     13 *
     14 **/
     15 
     16 #include "PcieInit.h"
     17 #include <Library/UefiBootServicesTableLib.h>
     18 #include <Library/PcdLib.h>
     19 #include <Library/OemMiscLib.h>
     20 #include <Library/PlatformPciLib.h>
     21 
     22 
     23 extern VOID PcieRegWrite(UINT32 Port, UINTN Offset, UINT32 Value);
     24 extern EFI_STATUS PciePortReset(UINT32 HostBridgeNum, UINT32 Port);
     25 extern EFI_STATUS PciePortInit (UINT32 soctype, UINT32 HostBridgeNum, PCIE_DRIVER_CFG *PcieCfg);
     26 
     27 PCIE_DRIVER_CFG gastr_pcie_driver_cfg[PCIE_MAX_ROOTBRIDGE] =
     28 {
     29     //Port 0
     30     {
     31         0x0,                        //Portindex
     32 
     33         {
     34             PCIE_ROOT_COMPLEX,      //PortType
     35             PCIE_WITDH_X8,          //PortWidth
     36             PCIE_GEN3_0,            //PortGen
     37         }, //PortInfo
     38 
     39     },
     40 
     41     //Port 1
     42     {
     43         0x1,                        //Portindex
     44         {
     45             PCIE_ROOT_COMPLEX,      //PortType
     46             PCIE_WITDH_X8,          //PortWidth
     47             PCIE_GEN3_0,            //PortGen
     48         },
     49 
     50     },
     51 
     52     //Port 2
     53     {
     54         0x2,                        //Portindex
     55         {
     56             PCIE_ROOT_COMPLEX,      //PortType
     57             PCIE_WITDH_X8,          //PortWidth
     58             PCIE_GEN3_0,            //PortGen
     59         },
     60 
     61     },
     62 
     63     //Port 3
     64     {
     65         0x3,                        //Portindex
     66         {
     67             PCIE_ROOT_COMPLEX,      //PortType
     68             PCIE_WITDH_X8,          //PortWidth
     69             PCIE_GEN3_0,            //PortGen
     70         },
     71 
     72     },
     73     //Port 4
     74     {
     75         0x4,                        //Portindex
     76         {
     77             PCIE_ROOT_COMPLEX,      //PortType
     78             PCIE_WITDH_X8,          //PortWidth
     79             PCIE_GEN3_0,            //PortGen
     80         },
     81 
     82     },
     83     //Port 5
     84     {
     85         0x5,                        //Portindex
     86         {
     87             PCIE_ROOT_COMPLEX,      //PortType
     88             PCIE_WITDH_X8,          //PortWidth
     89             PCIE_GEN3_0,            //PortGen
     90         },
     91 
     92     },
     93     //Port 6
     94     {
     95         0x6,                        //Portindex
     96         {
     97             PCIE_ROOT_COMPLEX,      //PortType
     98             PCIE_WITDH_X8,          //PortWidth
     99             PCIE_GEN3_0,            //PortGen
    100         },
    101 
    102     },
    103     //Port 7
    104     {
    105         0x7,                        //Portindex
    106         {
    107             PCIE_ROOT_COMPLEX,      //PortType
    108             PCIE_WITDH_X8,          //PortWidth
    109             PCIE_GEN3_0,            //PortGen
    110         },
    111 
    112     },
    113 };
    114 
    115 EFI_STATUS
    116 PcieInitEntry (
    117   IN EFI_HANDLE                 ImageHandle,
    118   IN EFI_SYSTEM_TABLE           *SystemTable
    119   )
    120 
    121 {
    122     UINT32             Port;
    123     EFI_STATUS         Status = EFI_SUCCESS;
    124     UINT32             HostBridgeNum = 0;
    125     UINT32             soctype = 0;
    126     UINT32       PcieRootBridgeMask;
    127 
    128 
    129     if (!OemIsMpBoot())
    130     {
    131         PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask);
    132     }
    133     else
    134     {
    135         PcieRootBridgeMask = PcdGet32(PcdPcieRootBridgeMask2P);
    136     }
    137 
    138     soctype = PcdGet32(Pcdsoctype);
    139     for (HostBridgeNum = 0; HostBridgeNum < PCIE_MAX_HOSTBRIDGE; HostBridgeNum++) {
    140         for (Port = 0; Port < PCIE_MAX_ROOTBRIDGE; Port++) {
    141             /*
    142                Host Bridge may contain lots of root bridges.
    143                Each Host bridge have PCIE_MAX_ROOTBRIDGE root bridges
    144                PcieRootBridgeMask have PCIE_MAX_ROOTBRIDGE*HostBridgeNum bits,
    145                and each bit stands for this PCIe Port is enable or not
    146             */
    147             if (!(((( PcieRootBridgeMask >> (PCIE_MAX_ROOTBRIDGE * HostBridgeNum))) >> Port) & 0x1)) {
    148                 continue;
    149             }
    150 
    151             Status = PciePortInit(soctype, HostBridgeNum, &gastr_pcie_driver_cfg[Port]);
    152             if(EFI_ERROR(Status))
    153             {
    154                 DEBUG((EFI_D_ERROR, "HostBridge %d, Pcie Port %d Init Failed! \n", HostBridgeNum, Port));
    155             }
    156 
    157         }
    158     }
    159 
    160 
    161     return EFI_SUCCESS;
    162 
    163 }
    164 
    165 
    166