1 /* tc-sparc.c -- Assemble for the SPARC 2 Copyright (C) 1989-2016 Free Software Foundation, Inc. 3 This file is part of GAS, the GNU Assembler. 4 5 GAS is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 3, or (at your option) 8 any later version. 9 10 GAS is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 15 You should have received a copy of the GNU General Public 16 License along with GAS; see the file COPYING. If not, write 17 to the Free Software Foundation, 51 Franklin Street - Fifth Floor, 18 Boston, MA 02110-1301, USA. */ 19 20 #include "as.h" 21 #include "safe-ctype.h" 22 #include "subsegs.h" 23 24 #include "opcode/sparc.h" 25 #include "dw2gencfi.h" 26 27 #ifdef OBJ_ELF 28 #include "elf/sparc.h" 29 #include "dwarf2dbg.h" 30 #endif 31 32 /* Some ancient Sun C compilers would not take such hex constants as 33 unsigned, and would end up sign-extending them to form an offsetT, 34 so use these constants instead. */ 35 #define U0xffffffff ((((unsigned long) 1 << 16) << 16) - 1) 36 #define U0x80000000 ((((unsigned long) 1 << 16) << 15)) 37 38 static int sparc_ip (char *, const struct sparc_opcode **); 39 static int parse_keyword_arg (int (*) (const char *), char **, int *); 40 static int parse_const_expr_arg (char **, int *); 41 static int get_expression (char *); 42 43 /* Default architecture. */ 44 /* ??? The default value should be V8, but sparclite support was added 45 by making it the default. GCC now passes -Asparclite, so maybe sometime in 46 the future we can set this to V8. */ 47 #ifndef DEFAULT_ARCH 48 #define DEFAULT_ARCH "sparclite" 49 #endif 50 static const char *default_arch = DEFAULT_ARCH; 51 52 /* Non-zero if the initial values of `max_architecture' and `sparc_arch_size' 53 have been set. */ 54 static int default_init_p; 55 56 /* Current architecture. We don't bump up unless necessary. */ 57 static enum sparc_opcode_arch_val current_architecture = SPARC_OPCODE_ARCH_V6; 58 59 /* The maximum architecture level we can bump up to. 60 In a 32 bit environment, don't allow bumping up to v9 by default. 61 The native assembler works this way. The user is required to pass 62 an explicit argument before we'll create v9 object files. However, if 63 we don't see any v9 insns, a v8plus object file is not created. */ 64 static enum sparc_opcode_arch_val max_architecture; 65 66 /* Either 32 or 64, selects file format. */ 67 static int sparc_arch_size; 68 /* Initial (default) value, recorded separately in case a user option 69 changes the value before md_show_usage is called. */ 70 static int default_arch_size; 71 72 #ifdef OBJ_ELF 73 /* The currently selected v9 memory model. Currently only used for 74 ELF. */ 75 static enum { MM_TSO, MM_PSO, MM_RMO } sparc_memory_model = MM_RMO; 76 77 #ifndef TE_SOLARIS 78 /* Bitmask of instruction types seen so far, used to populate the 79 GNU attributes section with hwcap information. */ 80 static bfd_uint64_t hwcap_seen; 81 #endif 82 #endif 83 84 static bfd_uint64_t hwcap_allowed; 85 86 static int architecture_requested; 87 static int warn_on_bump; 88 89 /* If warn_on_bump and the needed architecture is higher than this 90 architecture, issue a warning. */ 91 static enum sparc_opcode_arch_val warn_after_architecture; 92 93 /* Non-zero if as should generate error if an undeclared g[23] register 94 has been used in -64. */ 95 static int no_undeclared_regs; 96 97 /* Non-zero if we should try to relax jumps and calls. */ 98 static int sparc_relax; 99 100 /* Non-zero if we are generating PIC code. */ 101 int sparc_pic_code; 102 103 /* Non-zero if we should give an error when misaligned data is seen. */ 104 static int enforce_aligned_data; 105 106 extern int target_big_endian; 107 108 static int target_little_endian_data; 109 110 /* Symbols for global registers on v9. */ 111 static symbolS *globals[8]; 112 113 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ 114 int sparc_cie_data_alignment; 115 116 /* V9 and 86x have big and little endian data, but instructions are always big 117 endian. The sparclet has bi-endian support but both data and insns have 118 the same endianness. Global `target_big_endian' is used for data. 119 The following macro is used for instructions. */ 120 #ifndef INSN_BIG_ENDIAN 121 #define INSN_BIG_ENDIAN (target_big_endian \ 122 || default_arch_type == sparc86x \ 123 || SPARC_OPCODE_ARCH_V9_P (max_architecture)) 124 #endif 125 126 /* Handle of the OPCODE hash table. */ 127 static struct hash_control *op_hash; 128 129 static void s_data1 (void); 130 static void s_seg (int); 131 static void s_proc (int); 132 static void s_reserve (int); 133 static void s_common (int); 134 static void s_empty (int); 135 static void s_uacons (int); 136 static void s_ncons (int); 137 #ifdef OBJ_ELF 138 static void s_register (int); 139 #endif 140 141 const pseudo_typeS md_pseudo_table[] = 142 { 143 {"align", s_align_bytes, 0}, /* Defaulting is invalid (0). */ 144 {"common", s_common, 0}, 145 {"empty", s_empty, 0}, 146 {"global", s_globl, 0}, 147 {"half", cons, 2}, 148 {"nword", s_ncons, 0}, 149 {"optim", s_ignore, 0}, 150 {"proc", s_proc, 0}, 151 {"reserve", s_reserve, 0}, 152 {"seg", s_seg, 0}, 153 {"skip", s_space, 0}, 154 {"word", cons, 4}, 155 {"xword", cons, 8}, 156 {"uahalf", s_uacons, 2}, 157 {"uaword", s_uacons, 4}, 158 {"uaxword", s_uacons, 8}, 159 #ifdef OBJ_ELF 160 /* These are specific to sparc/svr4. */ 161 {"2byte", s_uacons, 2}, 162 {"4byte", s_uacons, 4}, 163 {"8byte", s_uacons, 8}, 164 {"register", s_register, 0}, 165 #endif 166 {NULL, 0, 0}, 167 }; 168 169 /* This array holds the chars that always start a comment. If the 170 pre-processor is disabled, these aren't very useful. */ 171 const char comment_chars[] = "!"; /* JF removed '|' from 172 comment_chars. */ 173 174 /* This array holds the chars that only start a comment at the beginning of 175 a line. If the line seems to have the form '# 123 filename' 176 .line and .file directives will appear in the pre-processed output. */ 177 /* Note that input_file.c hand checks for '#' at the beginning of the 178 first line of the input file. This is because the compiler outputs 179 #NO_APP at the beginning of its output. */ 180 /* Also note that comments started like this one will always 181 work if '/' isn't otherwise defined. */ 182 const char line_comment_chars[] = "#"; 183 184 const char line_separator_chars[] = ";"; 185 186 /* Chars that can be used to separate mant from exp in floating point 187 nums. */ 188 const char EXP_CHARS[] = "eE"; 189 190 /* Chars that mean this number is a floating point constant. 191 As in 0f12.456 192 or 0d1.2345e12 */ 193 const char FLT_CHARS[] = "rRsSfFdDxXpP"; 194 195 /* Also be aware that MAXIMUM_NUMBER_OF_CHARS_FOR_FLOAT may have to be 196 changed in read.c. Ideally it shouldn't have to know about it at all, 197 but nothing is ideal around here. */ 198 199 #define isoctal(c) ((unsigned) ((c) - '0') < 8) 200 201 struct sparc_it 202 { 203 const char *error; 204 unsigned long opcode; 205 struct nlist *nlistp; 206 expressionS exp; 207 expressionS exp2; 208 int pcrel; 209 bfd_reloc_code_real_type reloc; 210 }; 211 212 struct sparc_it the_insn, set_insn; 213 214 static void output_insn (const struct sparc_opcode *, struct sparc_it *); 215 216 /* Table of arguments to -A. 218 The sparc_opcode_arch table in sparc-opc.c is insufficient and incorrect 219 for this use. That table is for opcodes only. This table is for opcodes 220 and file formats. */ 221 222 enum sparc_arch_types {v6, v7, v8, leon, sparclet, sparclite, sparc86x, v8plus, 223 v8plusa, v9, v9a, v9b, v9_64}; 224 225 /* Hardware capability sets, used to keep sparc_arch_table easy to 226 read. */ 227 #define HWS_V8 HWCAP_MUL32 | HWCAP_DIV32 | HWCAP_FSMULD 228 #define HWS_V9 HWS_V8 | HWCAP_POPC 229 #define HWS_VA HWS_V9 | HWCAP_VIS 230 #define HWS_VB HWS_VA | HWCAP_VIS2 231 #define HWS_VC HWS_VB | HWCAP_ASI_BLK_INIT 232 #define HWS_VD HWS_VC | HWCAP_FMAF | HWCAP_VIS3 | HWCAP_HPC 233 #define HWS_VE HWS_VD \ 234 | HWCAP_AES | HWCAP_DES | HWCAP_KASUMI | HWCAP_CAMELLIA \ 235 | HWCAP_MD5 | HWCAP_SHA1 | HWCAP_SHA256 |HWCAP_SHA512 | HWCAP_MPMUL \ 236 | HWCAP_MONT | HWCAP_CRC32C | HWCAP_CBCOND | HWCAP_PAUSE 237 #define HWS_VV HWS_VE | HWCAP_FJFMAU | HWCAP_IMA 238 #define HWS_VM HWS_VV 239 240 #define HWS2_VM \ 241 HWCAP2_VIS3B | HWCAP2_ADP | HWCAP2_SPARC5 | HWCAP2_MWAIT \ 242 | HWCAP2_XMPMUL | HWCAP2_XMONT 243 244 static struct sparc_arch { 245 const char *name; 246 const char *opcode_arch; 247 enum sparc_arch_types arch_type; 248 /* Default word size, as specified during configuration. 249 A value of zero means can't be used to specify default architecture. */ 250 int default_arch_size; 251 /* Allowable arg to -A? */ 252 int user_option_p; 253 int hwcap_allowed; 254 int hwcap2_allowed; 255 } sparc_arch_table[] = { 256 { "v6", "v6", v6, 0, 1, 0, 0 }, 257 { "v7", "v7", v7, 0, 1, 0, 0 }, 258 { "v8", "v8", v8, 32, 1, HWS_V8, 0 }, 259 { "v8a", "v8", v8, 32, 1, HWS_V8, 0 }, 260 { "sparc", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 261 { "sparcvis", "v9a", v9, 0, 1, HWS_VA, 0 }, 262 { "sparcvis2", "v9b", v9, 0, 1, HWS_VB, 0 }, 263 { "sparcfmaf", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF, 0 }, 264 { "sparcima", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_IMA, 0 }, 265 { "sparcvis3", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC, 0 }, 266 { "sparcvis3r", "v9b", v9, 0, 1, HWS_VB|HWCAP_FMAF|HWCAP_VIS3|HWCAP_HPC|HWCAP_FJFMAU, 0 }, 267 268 { "sparc4", "v9v", v9, 0, 1, HWS_VV, 0 }, 269 { "sparc5", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, 270 271 { "leon", "leon", leon, 32, 1, HWS_V8, 0 }, 272 { "sparclet", "sparclet", sparclet, 32, 1, HWS_V8, 0 }, 273 { "sparclite", "sparclite", sparclite, 32, 1, HWS_V8, 0 }, 274 { "sparc86x", "sparclite", sparc86x, 32, 1, HWS_V8, 0 }, 275 276 { "v8plus", "v9", v9, 0, 1, HWCAP_V8PLUS|HWS_V9, 0 }, 277 { "v8plusa", "v9a", v9, 0, 1, HWCAP_V8PLUS|HWS_VA, 0 }, 278 { "v8plusb", "v9b", v9, 0, 1, HWCAP_V8PLUS|HWS_VB, 0 }, 279 { "v8plusc", "v9c", v9, 0, 1, HWCAP_V8PLUS|HWS_VC, 0 }, 280 { "v8plusd", "v9d", v9, 0, 1, HWCAP_V8PLUS|HWS_VD, 0 }, 281 { "v8pluse", "v9e", v9, 0, 1, HWCAP_V8PLUS|HWS_VE, 0 }, 282 { "v8plusv", "v9v", v9, 0, 1, HWCAP_V8PLUS|HWS_VV, 0 }, 283 { "v8plusm", "v9m", v9, 0, 1, HWCAP_V8PLUS|HWS_VM, 0 }, 284 285 { "v9", "v9", v9, 0, 1, HWS_V9, 0 }, 286 { "v9a", "v9a", v9, 0, 1, HWS_VA, 0 }, 287 { "v9b", "v9b", v9, 0, 1, HWS_VB, 0 }, 288 { "v9c", "v9c", v9, 0, 1, HWS_VC, 0 }, 289 { "v9d", "v9d", v9, 0, 1, HWS_VD, 0 }, 290 { "v9e", "v9e", v9, 0, 1, HWS_VE, 0 }, 291 { "v9v", "v9v", v9, 0, 1, HWS_VV, 0 }, 292 { "v9m", "v9m", v9, 0, 1, HWS_VM, HWS2_VM }, 293 294 /* This exists to allow configure.tgt to pass one 295 value to specify both the default machine and default word size. */ 296 { "v9-64", "v9", v9, 64, 0, HWS_V9, 0 }, 297 { NULL, NULL, v8, 0, 0, 0, 0 } 298 }; 299 300 /* Variant of default_arch */ 301 static enum sparc_arch_types default_arch_type; 302 303 static struct sparc_arch * 304 lookup_arch (const char *name) 305 { 306 struct sparc_arch *sa; 307 308 for (sa = &sparc_arch_table[0]; sa->name != NULL; sa++) 309 if (strcmp (sa->name, name) == 0) 310 break; 311 if (sa->name == NULL) 312 return NULL; 313 return sa; 314 } 315 316 /* Initialize the default opcode arch and word size from the default 317 architecture name. */ 318 319 static void 320 init_default_arch (void) 321 { 322 struct sparc_arch *sa = lookup_arch (default_arch); 323 324 if (sa == NULL 325 || sa->default_arch_size == 0) 326 as_fatal (_("Invalid default architecture, broken assembler.")); 327 328 max_architecture = sparc_opcode_lookup_arch (sa->opcode_arch); 329 if (max_architecture == SPARC_OPCODE_ARCH_BAD) 330 as_fatal (_("Bad opcode table, broken assembler.")); 331 default_arch_size = sparc_arch_size = sa->default_arch_size; 332 default_init_p = 1; 333 default_arch_type = sa->arch_type; 334 } 335 336 /* Called by TARGET_FORMAT. */ 337 338 const char * 339 sparc_target_format (void) 340 { 341 /* We don't get a chance to initialize anything before we're called, 342 so handle that now. */ 343 if (! default_init_p) 344 init_default_arch (); 345 346 #ifdef OBJ_AOUT 347 #ifdef TE_NetBSD 348 return "a.out-sparc-netbsd"; 349 #else 350 #ifdef TE_SPARCAOUT 351 if (target_big_endian) 352 return "a.out-sunos-big"; 353 else if (default_arch_type == sparc86x && target_little_endian_data) 354 return "a.out-sunos-big"; 355 else 356 return "a.out-sparc-little"; 357 #else 358 return "a.out-sunos-big"; 359 #endif 360 #endif 361 #endif 362 363 #ifdef OBJ_BOUT 364 return "b.out.big"; 365 #endif 366 367 #ifdef OBJ_COFF 368 #ifdef TE_LYNX 369 return "coff-sparc-lynx"; 370 #else 371 return "coff-sparc"; 372 #endif 373 #endif 374 375 #ifdef TE_VXWORKS 376 return "elf32-sparc-vxworks"; 377 #endif 378 379 #ifdef OBJ_ELF 380 return sparc_arch_size == 64 ? ELF64_TARGET_FORMAT : ELF_TARGET_FORMAT; 381 #endif 382 383 abort (); 384 } 385 386 /* md_parse_option 388 * Invocation line includes a switch not recognized by the base assembler. 389 * See if it's a processor-specific option. These are: 390 * 391 * -bump 392 * Warn on architecture bumps. See also -A. 393 * 394 * -Av6, -Av7, -Av8, -Aleon, -Asparclite, -Asparclet 395 * Standard 32 bit architectures. 396 * -Av9, -Av9a, -Av9b 397 * Sparc64 in either a 32 or 64 bit world (-32/-64 says which). 398 * This used to only mean 64 bits, but properly specifying it 399 * complicated gcc's ASM_SPECs, so now opcode selection is 400 * specified orthogonally to word size (except when specifying 401 * the default, but that is an internal implementation detail). 402 * -Av8plus, -Av8plusa, -Av8plusb 403 * Same as -Av9{,a,b}. 404 * -xarch=v8plus, -xarch=v8plusa, -xarch=v8plusb 405 * Same as -Av8plus{,a,b} -32, for compatibility with Sun's 406 * assembler. 407 * -xarch=v9, -xarch=v9a, -xarch=v9b 408 * Same as -Av9{,a,b} -64, for compatibility with Sun's 409 * assembler. 410 * 411 * Select the architecture and possibly the file format. 412 * Instructions or features not supported by the selected 413 * architecture cause fatal errors. 414 * 415 * The default is to start at v6, and bump the architecture up 416 * whenever an instruction is seen at a higher level. In 32 bit 417 * environments, v9 is not bumped up to, the user must pass 418 * -Av8plus{,a,b}. 419 * 420 * If -bump is specified, a warning is printing when bumping to 421 * higher levels. 422 * 423 * If an architecture is specified, all instructions must match 424 * that architecture. Any higher level instructions are flagged 425 * as errors. Note that in the 32 bit environment specifying 426 * -Av8plus does not automatically create a v8plus object file, a 427 * v9 insn must be seen. 428 * 429 * If both an architecture and -bump are specified, the 430 * architecture starts at the specified level, but bumps are 431 * warnings. Note that we can't set `current_architecture' to 432 * the requested level in this case: in the 32 bit environment, 433 * we still must avoid creating v8plus object files unless v9 434 * insns are seen. 435 * 436 * Note: 437 * Bumping between incompatible architectures is always an 438 * error. For example, from sparclite to v9. 439 */ 440 441 #ifdef OBJ_ELF 442 const char *md_shortopts = "A:K:VQ:sq"; 443 #else 444 #ifdef OBJ_AOUT 445 const char *md_shortopts = "A:k"; 446 #else 447 const char *md_shortopts = "A:"; 448 #endif 449 #endif 450 struct option md_longopts[] = { 451 #define OPTION_BUMP (OPTION_MD_BASE) 452 {"bump", no_argument, NULL, OPTION_BUMP}, 453 #define OPTION_SPARC (OPTION_MD_BASE + 1) 454 {"sparc", no_argument, NULL, OPTION_SPARC}, 455 #define OPTION_XARCH (OPTION_MD_BASE + 2) 456 {"xarch", required_argument, NULL, OPTION_XARCH}, 457 #ifdef OBJ_ELF 458 #define OPTION_32 (OPTION_MD_BASE + 3) 459 {"32", no_argument, NULL, OPTION_32}, 460 #define OPTION_64 (OPTION_MD_BASE + 4) 461 {"64", no_argument, NULL, OPTION_64}, 462 #define OPTION_TSO (OPTION_MD_BASE + 5) 463 {"TSO", no_argument, NULL, OPTION_TSO}, 464 #define OPTION_PSO (OPTION_MD_BASE + 6) 465 {"PSO", no_argument, NULL, OPTION_PSO}, 466 #define OPTION_RMO (OPTION_MD_BASE + 7) 467 {"RMO", no_argument, NULL, OPTION_RMO}, 468 #endif 469 #ifdef SPARC_BIENDIAN 470 #define OPTION_LITTLE_ENDIAN (OPTION_MD_BASE + 8) 471 {"EL", no_argument, NULL, OPTION_LITTLE_ENDIAN}, 472 #define OPTION_BIG_ENDIAN (OPTION_MD_BASE + 9) 473 {"EB", no_argument, NULL, OPTION_BIG_ENDIAN}, 474 #endif 475 #define OPTION_ENFORCE_ALIGNED_DATA (OPTION_MD_BASE + 10) 476 {"enforce-aligned-data", no_argument, NULL, OPTION_ENFORCE_ALIGNED_DATA}, 477 #define OPTION_LITTLE_ENDIAN_DATA (OPTION_MD_BASE + 11) 478 {"little-endian-data", no_argument, NULL, OPTION_LITTLE_ENDIAN_DATA}, 479 #ifdef OBJ_ELF 480 #define OPTION_NO_UNDECLARED_REGS (OPTION_MD_BASE + 12) 481 {"no-undeclared-regs", no_argument, NULL, OPTION_NO_UNDECLARED_REGS}, 482 #define OPTION_UNDECLARED_REGS (OPTION_MD_BASE + 13) 483 {"undeclared-regs", no_argument, NULL, OPTION_UNDECLARED_REGS}, 484 #endif 485 #define OPTION_RELAX (OPTION_MD_BASE + 14) 486 {"relax", no_argument, NULL, OPTION_RELAX}, 487 #define OPTION_NO_RELAX (OPTION_MD_BASE + 15) 488 {"no-relax", no_argument, NULL, OPTION_NO_RELAX}, 489 {NULL, no_argument, NULL, 0} 490 }; 491 492 size_t md_longopts_size = sizeof (md_longopts); 493 494 int 495 md_parse_option (int c, const char *arg) 496 { 497 /* We don't get a chance to initialize anything before we're called, 498 so handle that now. */ 499 if (! default_init_p) 500 init_default_arch (); 501 502 switch (c) 503 { 504 case OPTION_BUMP: 505 warn_on_bump = 1; 506 warn_after_architecture = SPARC_OPCODE_ARCH_V6; 507 break; 508 509 case OPTION_XARCH: 510 #ifdef OBJ_ELF 511 if (!strncmp (arg, "v9", 2)) 512 md_parse_option (OPTION_64, NULL); 513 else 514 { 515 if (!strncmp (arg, "v8", 2) 516 || !strncmp (arg, "v7", 2) 517 || !strncmp (arg, "v6", 2) 518 || !strcmp (arg, "sparclet") 519 || !strcmp (arg, "sparclite") 520 || !strcmp (arg, "sparc86x")) 521 md_parse_option (OPTION_32, NULL); 522 } 523 #endif 524 /* Fall through. */ 525 526 case 'A': 527 { 528 struct sparc_arch *sa; 529 enum sparc_opcode_arch_val opcode_arch; 530 531 sa = lookup_arch (arg); 532 if (sa == NULL 533 || ! sa->user_option_p) 534 { 535 if (c == OPTION_XARCH) 536 as_bad (_("invalid architecture -xarch=%s"), arg); 537 else 538 as_bad (_("invalid architecture -A%s"), arg); 539 return 0; 540 } 541 542 opcode_arch = sparc_opcode_lookup_arch (sa->opcode_arch); 543 if (opcode_arch == SPARC_OPCODE_ARCH_BAD) 544 as_fatal (_("Bad opcode table, broken assembler.")); 545 546 if (!architecture_requested 547 || opcode_arch > max_architecture) 548 max_architecture = opcode_arch; 549 hwcap_allowed 550 |= (((bfd_uint64_t) sa->hwcap2_allowed) << 32) | sa->hwcap_allowed; 551 architecture_requested = 1; 552 } 553 break; 554 555 case OPTION_SPARC: 556 /* Ignore -sparc, used by SunOS make default .s.o rule. */ 557 break; 558 559 case OPTION_ENFORCE_ALIGNED_DATA: 560 enforce_aligned_data = 1; 561 break; 562 563 #ifdef SPARC_BIENDIAN 564 case OPTION_LITTLE_ENDIAN: 565 target_big_endian = 0; 566 if (default_arch_type != sparclet) 567 as_fatal ("This target does not support -EL"); 568 break; 569 case OPTION_LITTLE_ENDIAN_DATA: 570 target_little_endian_data = 1; 571 target_big_endian = 0; 572 if (default_arch_type != sparc86x 573 && default_arch_type != v9) 574 as_fatal ("This target does not support --little-endian-data"); 575 break; 576 case OPTION_BIG_ENDIAN: 577 target_big_endian = 1; 578 break; 579 #endif 580 581 #ifdef OBJ_AOUT 582 case 'k': 583 sparc_pic_code = 1; 584 break; 585 #endif 586 587 #ifdef OBJ_ELF 588 case OPTION_32: 589 case OPTION_64: 590 { 591 const char **list, **l; 592 593 sparc_arch_size = c == OPTION_32 ? 32 : 64; 594 list = bfd_target_list (); 595 for (l = list; *l != NULL; l++) 596 { 597 if (sparc_arch_size == 32) 598 { 599 if (CONST_STRNEQ (*l, "elf32-sparc")) 600 break; 601 } 602 else 603 { 604 if (CONST_STRNEQ (*l, "elf64-sparc")) 605 break; 606 } 607 } 608 if (*l == NULL) 609 as_fatal (_("No compiled in support for %d bit object file format"), 610 sparc_arch_size); 611 free (list); 612 613 if (sparc_arch_size == 64 614 && max_architecture < SPARC_OPCODE_ARCH_V9) 615 max_architecture = SPARC_OPCODE_ARCH_V9; 616 } 617 break; 618 619 case OPTION_TSO: 620 sparc_memory_model = MM_TSO; 621 break; 622 623 case OPTION_PSO: 624 sparc_memory_model = MM_PSO; 625 break; 626 627 case OPTION_RMO: 628 sparc_memory_model = MM_RMO; 629 break; 630 631 case 'V': 632 print_version_id (); 633 break; 634 635 case 'Q': 636 /* Qy - do emit .comment 637 Qn - do not emit .comment. */ 638 break; 639 640 case 's': 641 /* Use .stab instead of .stab.excl. */ 642 break; 643 644 case 'q': 645 /* quick -- Native assembler does fewer checks. */ 646 break; 647 648 case 'K': 649 if (strcmp (arg, "PIC") != 0) 650 as_warn (_("Unrecognized option following -K")); 651 else 652 sparc_pic_code = 1; 653 break; 654 655 case OPTION_NO_UNDECLARED_REGS: 656 no_undeclared_regs = 1; 657 break; 658 659 case OPTION_UNDECLARED_REGS: 660 no_undeclared_regs = 0; 661 break; 662 #endif 663 664 case OPTION_RELAX: 665 sparc_relax = 1; 666 break; 667 668 case OPTION_NO_RELAX: 669 sparc_relax = 0; 670 break; 671 672 default: 673 return 0; 674 } 675 676 return 1; 677 } 678 679 void 680 md_show_usage (FILE *stream) 681 { 682 const struct sparc_arch *arch; 683 int column; 684 685 /* We don't get a chance to initialize anything before we're called, 686 so handle that now. */ 687 if (! default_init_p) 688 init_default_arch (); 689 690 fprintf (stream, _("SPARC options:\n")); 691 column = 0; 692 for (arch = &sparc_arch_table[0]; arch->name; arch++) 693 { 694 if (!arch->user_option_p) 695 continue; 696 if (arch != &sparc_arch_table[0]) 697 fprintf (stream, " | "); 698 if (column + strlen (arch->name) > 70) 699 { 700 column = 0; 701 fputc ('\n', stream); 702 } 703 column += 5 + 2 + strlen (arch->name); 704 fprintf (stream, "-A%s", arch->name); 705 } 706 for (arch = &sparc_arch_table[0]; arch->name; arch++) 707 { 708 if (!arch->user_option_p) 709 continue; 710 fprintf (stream, " | "); 711 if (column + strlen (arch->name) > 65) 712 { 713 column = 0; 714 fputc ('\n', stream); 715 } 716 column += 5 + 7 + strlen (arch->name); 717 fprintf (stream, "-xarch=%s", arch->name); 718 } 719 fprintf (stream, _("\n\ 720 specify variant of SPARC architecture\n\ 721 -bump warn when assembler switches architectures\n\ 722 -sparc ignored\n\ 723 --enforce-aligned-data force .long, etc., to be aligned correctly\n\ 724 -relax relax jumps and branches (default)\n\ 725 -no-relax avoid changing any jumps and branches\n")); 726 #ifdef OBJ_AOUT 727 fprintf (stream, _("\ 728 -k generate PIC\n")); 729 #endif 730 #ifdef OBJ_ELF 731 fprintf (stream, _("\ 732 -32 create 32 bit object file\n\ 733 -64 create 64 bit object file\n")); 734 fprintf (stream, _("\ 735 [default is %d]\n"), default_arch_size); 736 fprintf (stream, _("\ 737 -TSO use Total Store Ordering\n\ 738 -PSO use Partial Store Ordering\n\ 739 -RMO use Relaxed Memory Ordering\n")); 740 fprintf (stream, _("\ 741 [default is %s]\n"), (default_arch_size == 64) ? "RMO" : "TSO"); 742 fprintf (stream, _("\ 743 -KPIC generate PIC\n\ 744 -V print assembler version number\n\ 745 -undeclared-regs ignore application global register usage without\n\ 746 appropriate .register directive (default)\n\ 747 -no-undeclared-regs force error on application global register usage\n\ 748 without appropriate .register directive\n\ 749 -q ignored\n\ 750 -Qy, -Qn ignored\n\ 751 -s ignored\n")); 752 #endif 753 #ifdef SPARC_BIENDIAN 754 fprintf (stream, _("\ 755 -EL generate code for a little endian machine\n\ 756 -EB generate code for a big endian machine\n\ 757 --little-endian-data generate code for a machine having big endian\n\ 758 instructions and little endian data.\n")); 759 #endif 760 } 761 762 /* Native operand size opcode translation. */ 764 static struct 765 { 766 const char *name; 767 const char *name32; 768 const char *name64; 769 } native_op_table[] = 770 { 771 {"ldn", "ld", "ldx"}, 772 {"ldna", "lda", "ldxa"}, 773 {"stn", "st", "stx"}, 774 {"stna", "sta", "stxa"}, 775 {"slln", "sll", "sllx"}, 776 {"srln", "srl", "srlx"}, 777 {"sran", "sra", "srax"}, 778 {"casn", "cas", "casx"}, 779 {"casna", "casa", "casxa"}, 780 {"clrn", "clr", "clrx"}, 781 {NULL, NULL, NULL}, 782 }; 783 784 /* sparc64 privileged and hyperprivileged registers. */ 786 787 struct priv_reg_entry 788 { 789 const char *name; 790 int regnum; 791 }; 792 793 struct priv_reg_entry priv_reg_table[] = 794 { 795 {"tpc", 0}, 796 {"tnpc", 1}, 797 {"tstate", 2}, 798 {"tt", 3}, 799 {"tick", 4}, 800 {"tba", 5}, 801 {"pstate", 6}, 802 {"tl", 7}, 803 {"pil", 8}, 804 {"cwp", 9}, 805 {"cansave", 10}, 806 {"canrestore", 11}, 807 {"cleanwin", 12}, 808 {"otherwin", 13}, 809 {"wstate", 14}, 810 {"fq", 15}, 811 {"gl", 16}, 812 {"pmcdper", 23}, 813 {"ver", 31}, 814 {NULL, -1}, /* End marker. */ 815 }; 816 817 struct priv_reg_entry hpriv_reg_table[] = 818 { 819 {"hpstate", 0}, 820 {"htstate", 1}, 821 {"hintp", 3}, 822 {"htba", 5}, 823 {"hver", 6}, 824 {"hmcdper", 23}, 825 {"hmcddfr", 24}, 826 {"hva_mask_nz", 27}, 827 {"hstick_offset", 28}, 828 {"hstick_enable", 29}, 829 {"hstick_cmpr", 31}, 830 {NULL, -1}, /* End marker. */ 831 }; 832 833 /* v9a or later specific ancillary state registers. */ 834 835 struct priv_reg_entry v9a_asr_table[] = 836 { 837 {"tick_cmpr", 23}, 838 {"sys_tick_cmpr", 25}, 839 {"sys_tick", 24}, 840 {"stick_cmpr", 25}, 841 {"stick", 24}, 842 {"softint_clear", 21}, 843 {"softint_set", 20}, 844 {"softint", 22}, 845 {"set_softint", 20}, 846 {"pause", 27}, 847 {"pic", 17}, 848 {"pcr", 16}, 849 {"mwait", 28}, 850 {"gsr", 19}, 851 {"dcr", 18}, 852 {"cfr", 26}, 853 {"clear_softint", 21}, 854 {NULL, -1}, /* End marker. */ 855 }; 856 857 static int 858 cmp_reg_entry (const void *parg, const void *qarg) 859 { 860 const struct priv_reg_entry *p = (const struct priv_reg_entry *) parg; 861 const struct priv_reg_entry *q = (const struct priv_reg_entry *) qarg; 862 863 if (p->name == q->name) 864 return 0; 865 else if (p->name == NULL) 866 return 1; 867 else if (q->name == NULL) 868 return -1; 869 else 870 return strcmp (q->name, p->name); 871 } 872 873 /* sparc %-pseudo-operations. */ 875 876 877 #define F_POP_V9 0x1 /* The pseudo-op is for v9 only. */ 878 #define F_POP_PCREL 0x2 /* The pseudo-op can be used in pc-relative 879 contexts. */ 880 #define F_POP_TLS_CALL 0x4 /* The pseudo-op marks a tls call. */ 881 #define F_POP_POSTFIX 0x8 /* The pseudo-op should appear after the 882 last operand of an 883 instruction. (Generally they can appear 884 anywhere an immediate operand is 885 expected. */ 886 struct pop_entry 887 { 888 /* The name as it appears in assembler. */ 889 const char *name; 890 /* The reloc this pseudo-op translates to. */ 891 int reloc; 892 /* Flags. See F_POP_* above. */ 893 int flags; 894 }; 895 896 struct pop_entry pop_table[] = 897 { 898 { "hix", BFD_RELOC_SPARC_HIX22, F_POP_V9 }, 899 { "lox", BFD_RELOC_SPARC_LOX10, F_POP_V9 }, 900 { "hi", BFD_RELOC_HI22, F_POP_PCREL }, 901 { "lo", BFD_RELOC_LO10, F_POP_PCREL }, 902 { "pc22", BFD_RELOC_SPARC_PC22, F_POP_PCREL }, 903 { "pc10", BFD_RELOC_SPARC_PC10, F_POP_PCREL }, 904 { "hh", BFD_RELOC_SPARC_HH22, F_POP_V9|F_POP_PCREL }, 905 { "hm", BFD_RELOC_SPARC_HM10, F_POP_V9|F_POP_PCREL }, 906 { "lm", BFD_RELOC_SPARC_LM22, F_POP_V9|F_POP_PCREL }, 907 { "h34", BFD_RELOC_SPARC_H34, F_POP_V9 }, 908 { "l34", BFD_RELOC_SPARC_L44, F_POP_V9 }, 909 { "h44", BFD_RELOC_SPARC_H44, F_POP_V9 }, 910 { "m44", BFD_RELOC_SPARC_M44, F_POP_V9 }, 911 { "l44", BFD_RELOC_SPARC_L44, F_POP_V9 }, 912 { "uhi", BFD_RELOC_SPARC_HH22, F_POP_V9 }, 913 { "ulo", BFD_RELOC_SPARC_HM10, F_POP_V9 }, 914 { "tgd_hi22", BFD_RELOC_SPARC_TLS_GD_HI22, 0 }, 915 { "tgd_lo10", BFD_RELOC_SPARC_TLS_GD_LO10, 0 }, 916 { "tldm_hi22", BFD_RELOC_SPARC_TLS_LDM_HI22, 0 }, 917 { "tldm_lo10", BFD_RELOC_SPARC_TLS_LDM_LO10, 0 }, 918 { "tldo_hix22", BFD_RELOC_SPARC_TLS_LDO_HIX22, 0 }, 919 { "tldo_lox10", BFD_RELOC_SPARC_TLS_LDO_LOX10, 0 }, 920 { "tie_hi22", BFD_RELOC_SPARC_TLS_IE_HI22, 0 }, 921 { "tie_lo10", BFD_RELOC_SPARC_TLS_IE_LO10, 0 }, 922 { "tle_hix22", BFD_RELOC_SPARC_TLS_LE_HIX22, 0 }, 923 { "tle_lox10", BFD_RELOC_SPARC_TLS_LE_LOX10, 0 }, 924 { "gdop_hix22", BFD_RELOC_SPARC_GOTDATA_OP_HIX22, 0 }, 925 { "gdop_lox10", BFD_RELOC_SPARC_GOTDATA_OP_LOX10, 0 }, 926 { "tgd_add", BFD_RELOC_SPARC_TLS_GD_ADD, F_POP_POSTFIX }, 927 { "tgd_call", BFD_RELOC_SPARC_TLS_GD_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 928 { "tldm_add", BFD_RELOC_SPARC_TLS_LDM_ADD, F_POP_POSTFIX }, 929 { "tldm_call", BFD_RELOC_SPARC_TLS_LDM_CALL, F_POP_POSTFIX|F_POP_TLS_CALL }, 930 { "tldo_add", BFD_RELOC_SPARC_TLS_LDO_ADD, F_POP_POSTFIX }, 931 { "tie_ldx", BFD_RELOC_SPARC_TLS_IE_LDX, F_POP_POSTFIX }, 932 { "tie_ld", BFD_RELOC_SPARC_TLS_IE_LD, F_POP_POSTFIX }, 933 { "tie_add", BFD_RELOC_SPARC_TLS_IE_ADD, F_POP_POSTFIX }, 934 { "gdop", BFD_RELOC_SPARC_GOTDATA_OP, F_POP_POSTFIX }, 935 { NULL, 0, 0 }, 936 }; 937 938 /* Table of %-names that can appear in a sparc assembly program. This 940 table is initialized in md_begin and contains entries for each 941 privileged/hyperprivileged/alternate register and %-pseudo-op. */ 942 943 enum perc_entry_type 944 { 945 perc_entry_none = 0, 946 perc_entry_reg, 947 perc_entry_post_pop, 948 perc_entry_imm_pop 949 }; 950 951 struct perc_entry 952 { 953 /* Entry type. */ 954 enum perc_entry_type type; 955 /* Name of the %-entity. */ 956 const char *name; 957 /* strlen (name). */ 958 int len; 959 /* Value. Either a pop or a reg depending on type.*/ 960 union 961 { 962 struct pop_entry *pop; 963 struct priv_reg_entry *reg; 964 }; 965 }; 966 967 #define NUM_PERC_ENTRIES \ 968 (((sizeof (priv_reg_table) / sizeof (priv_reg_table[0])) - 1) \ 969 + ((sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0])) - 1) \ 970 + ((sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0])) - 1) \ 971 + ((sizeof (pop_table) / sizeof (pop_table[0])) - 1) \ 972 + 1) 973 974 struct perc_entry perc_table[NUM_PERC_ENTRIES]; 975 976 static int 977 cmp_perc_entry (const void *parg, const void *qarg) 978 { 979 const struct perc_entry *p = (const struct perc_entry *) parg; 980 const struct perc_entry *q = (const struct perc_entry *) qarg; 981 982 if (p->name == q->name) 983 return 0; 984 else if (p->name == NULL) 985 return 1; 986 else if (q->name == NULL) 987 return -1; 988 else 989 return strcmp (q->name, p->name); 990 } 991 992 /* This function is called once, at assembler startup time. It should 994 set up all the tables, etc. that the MD part of the assembler will 995 need. */ 996 997 void 998 md_begin (void) 999 { 1000 const char *retval = NULL; 1001 int lose = 0; 1002 unsigned int i = 0; 1003 1004 /* We don't get a chance to initialize anything before md_parse_option 1005 is called, and it may not be called, so handle default initialization 1006 now if not already done. */ 1007 if (! default_init_p) 1008 init_default_arch (); 1009 1010 sparc_cie_data_alignment = sparc_arch_size == 64 ? -8 : -4; 1011 op_hash = hash_new (); 1012 1013 while (i < (unsigned int) sparc_num_opcodes) 1014 { 1015 const char *name = sparc_opcodes[i].name; 1016 retval = hash_insert (op_hash, name, (void *) &sparc_opcodes[i]); 1017 if (retval != NULL) 1018 { 1019 as_bad (_("Internal error: can't hash `%s': %s\n"), 1020 sparc_opcodes[i].name, retval); 1021 lose = 1; 1022 } 1023 do 1024 { 1025 if (sparc_opcodes[i].match & sparc_opcodes[i].lose) 1026 { 1027 as_bad (_("Internal error: losing opcode: `%s' \"%s\"\n"), 1028 sparc_opcodes[i].name, sparc_opcodes[i].args); 1029 lose = 1; 1030 } 1031 ++i; 1032 } 1033 while (i < (unsigned int) sparc_num_opcodes 1034 && !strcmp (sparc_opcodes[i].name, name)); 1035 } 1036 1037 for (i = 0; native_op_table[i].name; i++) 1038 { 1039 const struct sparc_opcode *insn; 1040 const char *name = ((sparc_arch_size == 32) 1041 ? native_op_table[i].name32 1042 : native_op_table[i].name64); 1043 insn = (struct sparc_opcode *) hash_find (op_hash, name); 1044 if (insn == NULL) 1045 { 1046 as_bad (_("Internal error: can't find opcode `%s' for `%s'\n"), 1047 name, native_op_table[i].name); 1048 lose = 1; 1049 } 1050 else 1051 { 1052 retval = hash_insert (op_hash, native_op_table[i].name, 1053 (void *) insn); 1054 if (retval != NULL) 1055 { 1056 as_bad (_("Internal error: can't hash `%s': %s\n"), 1057 sparc_opcodes[i].name, retval); 1058 lose = 1; 1059 } 1060 } 1061 } 1062 1063 if (lose) 1064 as_fatal (_("Broken assembler. No assembly attempted.")); 1065 1066 qsort (priv_reg_table, sizeof (priv_reg_table) / sizeof (priv_reg_table[0]), 1067 sizeof (priv_reg_table[0]), cmp_reg_entry); 1068 qsort (hpriv_reg_table, sizeof (hpriv_reg_table) / sizeof (hpriv_reg_table[0]), 1069 sizeof (hpriv_reg_table[0]), cmp_reg_entry); 1070 qsort (v9a_asr_table, sizeof (v9a_asr_table) / sizeof (v9a_asr_table[0]), 1071 sizeof (v9a_asr_table[0]), cmp_reg_entry); 1072 1073 /* If -bump, record the architecture level at which we start issuing 1074 warnings. The behaviour is different depending upon whether an 1075 architecture was explicitly specified. If it wasn't, we issue warnings 1076 for all upwards bumps. If it was, we don't start issuing warnings until 1077 we need to bump beyond the requested architecture or when we bump between 1078 conflicting architectures. */ 1079 1080 if (warn_on_bump 1081 && architecture_requested) 1082 { 1083 /* `max_architecture' records the requested architecture. 1084 Issue warnings if we go above it. */ 1085 warn_after_architecture = max_architecture; 1086 } 1087 1088 /* Find the highest architecture level that doesn't conflict with 1089 the requested one. */ 1090 1091 if (warn_on_bump 1092 || !architecture_requested) 1093 { 1094 enum sparc_opcode_arch_val current_max_architecture 1095 = max_architecture; 1096 1097 for (max_architecture = SPARC_OPCODE_ARCH_MAX; 1098 max_architecture > warn_after_architecture; 1099 --max_architecture) 1100 if (! SPARC_OPCODE_CONFLICT_P (max_architecture, 1101 current_max_architecture)) 1102 break; 1103 } 1104 1105 /* Prepare the tables of %-pseudo-ops. */ 1106 { 1107 struct priv_reg_entry *reg_tables[] 1108 = {priv_reg_table, hpriv_reg_table, v9a_asr_table, NULL}; 1109 struct priv_reg_entry **reg_table; 1110 int entry = 0; 1111 1112 /* Add registers. */ 1113 for (reg_table = reg_tables; reg_table[0]; reg_table++) 1114 { 1115 struct priv_reg_entry *reg; 1116 for (reg = *reg_table; reg->name; reg++) 1117 { 1118 struct perc_entry *p = &perc_table[entry++]; 1119 p->type = perc_entry_reg; 1120 p->name = reg->name; 1121 p->len = strlen (reg->name); 1122 p->reg = reg; 1123 } 1124 } 1125 1126 /* Add %-pseudo-ops. */ 1127 { 1128 struct pop_entry *pop; 1129 1130 for (pop = pop_table; pop->name; pop++) 1131 { 1132 struct perc_entry *p = &perc_table[entry++]; 1133 p->type = (pop->flags & F_POP_POSTFIX 1134 ? perc_entry_post_pop : perc_entry_imm_pop); 1135 p->name = pop->name; 1136 p->len = strlen (pop->name); 1137 p->pop = pop; 1138 } 1139 } 1140 1141 /* Last entry is the centinel. */ 1142 perc_table[entry].type = perc_entry_none; 1143 1144 qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]), 1145 sizeof (perc_table[0]), cmp_perc_entry); 1146 1147 } 1148 } 1149 1150 /* Called after all assembly has been done. */ 1151 1152 void 1153 sparc_md_end (void) 1154 { 1155 unsigned long mach = bfd_mach_sparc; 1156 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 1157 int hwcaps, hwcaps2; 1158 #endif 1159 1160 if (sparc_arch_size == 64) 1161 switch (current_architecture) 1162 { 1163 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v9a; break; 1164 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v9b; break; 1165 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v9c; break; 1166 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v9d; break; 1167 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v9e; break; 1168 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v9v; break; 1169 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v9m; break; 1170 default: mach = bfd_mach_sparc_v9; break; 1171 } 1172 else 1173 switch (current_architecture) 1174 { 1175 case SPARC_OPCODE_ARCH_SPARCLET: mach = bfd_mach_sparc_sparclet; break; 1176 case SPARC_OPCODE_ARCH_V9: mach = bfd_mach_sparc_v8plus; break; 1177 case SPARC_OPCODE_ARCH_V9A: mach = bfd_mach_sparc_v8plusa; break; 1178 case SPARC_OPCODE_ARCH_V9B: mach = bfd_mach_sparc_v8plusb; break; 1179 case SPARC_OPCODE_ARCH_V9C: mach = bfd_mach_sparc_v8plusc; break; 1180 case SPARC_OPCODE_ARCH_V9D: mach = bfd_mach_sparc_v8plusd; break; 1181 case SPARC_OPCODE_ARCH_V9E: mach = bfd_mach_sparc_v8pluse; break; 1182 case SPARC_OPCODE_ARCH_V9V: mach = bfd_mach_sparc_v8plusv; break; 1183 case SPARC_OPCODE_ARCH_V9M: mach = bfd_mach_sparc_v8plusm; break; 1184 /* The sparclite is treated like a normal sparc. Perhaps it shouldn't 1185 be but for now it is (since that's the way it's always been 1186 treated). */ 1187 default: break; 1188 } 1189 bfd_set_arch_mach (stdoutput, bfd_arch_sparc, mach); 1190 1191 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 1192 hwcaps = hwcap_seen & U0xffffffff; 1193 hwcaps2 = hwcap_seen >> 32; 1194 1195 if (hwcaps) 1196 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS, hwcaps); 1197 if (hwcaps2) 1198 bfd_elf_add_obj_attr_int (stdoutput, OBJ_ATTR_GNU, Tag_GNU_Sparc_HWCAPS2, hwcaps2); 1199 #endif 1200 } 1201 1202 /* Return non-zero if VAL is in the range -(MAX+1) to MAX. */ 1204 1205 static inline int 1206 in_signed_range (bfd_signed_vma val, bfd_signed_vma max) 1207 { 1208 if (max <= 0) 1209 abort (); 1210 /* Sign-extend the value from the architecture word size, so that 1211 0xffffffff is always considered -1 on sparc32. */ 1212 if (sparc_arch_size == 32) 1213 { 1214 bfd_signed_vma sign = (bfd_signed_vma) 1 << 31; 1215 val = ((val & U0xffffffff) ^ sign) - sign; 1216 } 1217 if (val > max) 1218 return 0; 1219 if (val < ~max) 1220 return 0; 1221 return 1; 1222 } 1223 1224 /* Return non-zero if VAL is in the range 0 to MAX. */ 1225 1226 static inline int 1227 in_unsigned_range (bfd_vma val, bfd_vma max) 1228 { 1229 if (val > max) 1230 return 0; 1231 return 1; 1232 } 1233 1234 /* Return non-zero if VAL is in the range -(MAX/2+1) to MAX. 1235 (e.g. -15 to +31). */ 1236 1237 static inline int 1238 in_bitfield_range (bfd_signed_vma val, bfd_signed_vma max) 1239 { 1240 if (max <= 0) 1241 abort (); 1242 if (val > max) 1243 return 0; 1244 if (val < ~(max >> 1)) 1245 return 0; 1246 return 1; 1247 } 1248 1249 static int 1250 sparc_ffs (unsigned int mask) 1251 { 1252 int i; 1253 1254 if (mask == 0) 1255 return -1; 1256 1257 for (i = 0; (mask & 1) == 0; ++i) 1258 mask >>= 1; 1259 return i; 1260 } 1261 1262 /* Implement big shift right. */ 1263 static bfd_vma 1264 BSR (bfd_vma val, int amount) 1265 { 1266 if (sizeof (bfd_vma) <= 4 && amount >= 32) 1267 as_fatal (_("Support for 64-bit arithmetic not compiled in.")); 1268 return val >> amount; 1269 } 1270 1271 /* For communication between sparc_ip and get_expression. */ 1273 static char *expr_end; 1274 1275 /* Values for `special_case'. 1276 Instructions that require wierd handling because they're longer than 1277 4 bytes. */ 1278 #define SPECIAL_CASE_NONE 0 1279 #define SPECIAL_CASE_SET 1 1280 #define SPECIAL_CASE_SETSW 2 1281 #define SPECIAL_CASE_SETX 3 1282 /* FIXME: sparc-opc.c doesn't have necessary "S" trigger to enable this. */ 1283 #define SPECIAL_CASE_FDIV 4 1284 1285 /* Bit masks of various insns. */ 1286 #define NOP_INSN 0x01000000 1287 #define OR_INSN 0x80100000 1288 #define XOR_INSN 0x80180000 1289 #define FMOVS_INSN 0x81A00020 1290 #define SETHI_INSN 0x01000000 1291 #define SLLX_INSN 0x81281000 1292 #define SRA_INSN 0x81380000 1293 1294 /* The last instruction to be assembled. */ 1295 static const struct sparc_opcode *last_insn; 1296 /* The assembled opcode of `last_insn'. */ 1297 static unsigned long last_opcode; 1298 1299 /* Handle the set and setuw synthetic instructions. */ 1301 1302 static void 1303 synthetize_setuw (const struct sparc_opcode *insn) 1304 { 1305 int need_hi22_p = 0; 1306 int rd = (the_insn.opcode & RD (~0)) >> 25; 1307 1308 if (the_insn.exp.X_op == O_constant) 1309 { 1310 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 1311 { 1312 if (sizeof (offsetT) > 4 1313 && (the_insn.exp.X_add_number < 0 1314 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1315 as_warn (_("set: number not in 0..4294967295 range")); 1316 } 1317 else 1318 { 1319 if (sizeof (offsetT) > 4 1320 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1321 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1322 as_warn (_("set: number not in -2147483648..4294967295 range")); 1323 the_insn.exp.X_add_number = (int) the_insn.exp.X_add_number; 1324 } 1325 } 1326 1327 /* See if operand is absolute and small; skip sethi if so. */ 1328 if (the_insn.exp.X_op != O_constant 1329 || the_insn.exp.X_add_number >= (1 << 12) 1330 || the_insn.exp.X_add_number < -(1 << 12)) 1331 { 1332 the_insn.opcode = (SETHI_INSN | RD (rd) 1333 | ((the_insn.exp.X_add_number >> 10) 1334 & (the_insn.exp.X_op == O_constant 1335 ? 0x3fffff : 0))); 1336 the_insn.reloc = (the_insn.exp.X_op != O_constant 1337 ? BFD_RELOC_HI22 : BFD_RELOC_NONE); 1338 output_insn (insn, &the_insn); 1339 need_hi22_p = 1; 1340 } 1341 1342 /* See if operand has no low-order bits; skip OR if so. */ 1343 if (the_insn.exp.X_op != O_constant 1344 || (need_hi22_p && (the_insn.exp.X_add_number & 0x3FF) != 0) 1345 || ! need_hi22_p) 1346 { 1347 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (rd) : 0) 1348 | RD (rd) | IMMED 1349 | (the_insn.exp.X_add_number 1350 & (the_insn.exp.X_op != O_constant 1351 ? 0 : need_hi22_p ? 0x3ff : 0x1fff))); 1352 the_insn.reloc = (the_insn.exp.X_op != O_constant 1353 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1354 output_insn (insn, &the_insn); 1355 } 1356 } 1357 1358 /* Handle the setsw synthetic instruction. */ 1359 1360 static void 1361 synthetize_setsw (const struct sparc_opcode *insn) 1362 { 1363 int low32, rd, opc; 1364 1365 rd = (the_insn.opcode & RD (~0)) >> 25; 1366 1367 if (the_insn.exp.X_op != O_constant) 1368 { 1369 synthetize_setuw (insn); 1370 1371 /* Need to sign extend it. */ 1372 the_insn.opcode = (SRA_INSN | RS1 (rd) | RD (rd)); 1373 the_insn.reloc = BFD_RELOC_NONE; 1374 output_insn (insn, &the_insn); 1375 return; 1376 } 1377 1378 if (sizeof (offsetT) > 4 1379 && (the_insn.exp.X_add_number < -(offsetT) U0x80000000 1380 || the_insn.exp.X_add_number > (offsetT) U0xffffffff)) 1381 as_warn (_("setsw: number not in -2147483648..4294967295 range")); 1382 1383 low32 = the_insn.exp.X_add_number; 1384 1385 if (low32 >= 0) 1386 { 1387 synthetize_setuw (insn); 1388 return; 1389 } 1390 1391 opc = OR_INSN; 1392 1393 the_insn.reloc = BFD_RELOC_NONE; 1394 /* See if operand is absolute and small; skip sethi if so. */ 1395 if (low32 < -(1 << 12)) 1396 { 1397 the_insn.opcode = (SETHI_INSN | RD (rd) 1398 | (((~the_insn.exp.X_add_number) >> 10) & 0x3fffff)); 1399 output_insn (insn, &the_insn); 1400 low32 = 0x1c00 | (low32 & 0x3ff); 1401 opc = RS1 (rd) | XOR_INSN; 1402 } 1403 1404 the_insn.opcode = (opc | RD (rd) | IMMED 1405 | (low32 & 0x1fff)); 1406 output_insn (insn, &the_insn); 1407 } 1408 1409 /* Handle the setx synthetic instruction. */ 1410 1411 static void 1412 synthetize_setx (const struct sparc_opcode *insn) 1413 { 1414 int upper32, lower32; 1415 int tmpreg = (the_insn.opcode & RS1 (~0)) >> 14; 1416 int dstreg = (the_insn.opcode & RD (~0)) >> 25; 1417 int upper_dstreg; 1418 int need_hh22_p = 0, need_hm10_p = 0, need_hi22_p = 0, need_lo10_p = 0; 1419 int need_xor10_p = 0; 1420 1421 #define SIGNEXT32(x) ((((x) & U0xffffffff) ^ U0x80000000) - U0x80000000) 1422 lower32 = SIGNEXT32 (the_insn.exp.X_add_number); 1423 upper32 = SIGNEXT32 (BSR (the_insn.exp.X_add_number, 32)); 1424 #undef SIGNEXT32 1425 1426 upper_dstreg = tmpreg; 1427 /* The tmp reg should not be the dst reg. */ 1428 if (tmpreg == dstreg) 1429 as_warn (_("setx: temporary register same as destination register")); 1430 1431 /* ??? Obviously there are other optimizations we can do 1432 (e.g. sethi+shift for 0x1f0000000) and perhaps we shouldn't be 1433 doing some of these. Later. If you do change things, try to 1434 change all of this to be table driven as well. */ 1435 /* What to output depends on the number if it's constant. 1436 Compute that first, then output what we've decided upon. */ 1437 if (the_insn.exp.X_op != O_constant) 1438 { 1439 if (sparc_arch_size == 32) 1440 { 1441 /* When arch size is 32, we want setx to be equivalent 1442 to setuw for anything but constants. */ 1443 the_insn.exp.X_add_number &= 0xffffffff; 1444 synthetize_setuw (insn); 1445 return; 1446 } 1447 need_hh22_p = need_hm10_p = need_hi22_p = need_lo10_p = 1; 1448 lower32 = 0; 1449 upper32 = 0; 1450 } 1451 else 1452 { 1453 /* Reset X_add_number, we've extracted it as upper32/lower32. 1454 Otherwise fixup_segment will complain about not being able to 1455 write an 8 byte number in a 4 byte field. */ 1456 the_insn.exp.X_add_number = 0; 1457 1458 /* Only need hh22 if `or' insn can't handle constant. */ 1459 if (upper32 < -(1 << 12) || upper32 >= (1 << 12)) 1460 need_hh22_p = 1; 1461 1462 /* Does bottom part (after sethi) have bits? */ 1463 if ((need_hh22_p && (upper32 & 0x3ff) != 0) 1464 /* No hh22, but does upper32 still have bits we can't set 1465 from lower32? */ 1466 || (! need_hh22_p && upper32 != 0 && upper32 != -1)) 1467 need_hm10_p = 1; 1468 1469 /* If the lower half is all zero, we build the upper half directly 1470 into the dst reg. */ 1471 if (lower32 != 0 1472 /* Need lower half if number is zero or 0xffffffff00000000. */ 1473 || (! need_hh22_p && ! need_hm10_p)) 1474 { 1475 /* No need for sethi if `or' insn can handle constant. */ 1476 if (lower32 < -(1 << 12) || lower32 >= (1 << 12) 1477 /* Note that we can't use a negative constant in the `or' 1478 insn unless the upper 32 bits are all ones. */ 1479 || (lower32 < 0 && upper32 != -1) 1480 || (lower32 >= 0 && upper32 == -1)) 1481 need_hi22_p = 1; 1482 1483 if (need_hi22_p && upper32 == -1) 1484 need_xor10_p = 1; 1485 1486 /* Does bottom part (after sethi) have bits? */ 1487 else if ((need_hi22_p && (lower32 & 0x3ff) != 0) 1488 /* No sethi. */ 1489 || (! need_hi22_p && (lower32 & 0x1fff) != 0) 1490 /* Need `or' if we didn't set anything else. */ 1491 || (! need_hi22_p && ! need_hh22_p && ! need_hm10_p)) 1492 need_lo10_p = 1; 1493 } 1494 else 1495 /* Output directly to dst reg if lower 32 bits are all zero. */ 1496 upper_dstreg = dstreg; 1497 } 1498 1499 if (!upper_dstreg && dstreg) 1500 as_warn (_("setx: illegal temporary register g0")); 1501 1502 if (need_hh22_p) 1503 { 1504 the_insn.opcode = (SETHI_INSN | RD (upper_dstreg) 1505 | ((upper32 >> 10) & 0x3fffff)); 1506 the_insn.reloc = (the_insn.exp.X_op != O_constant 1507 ? BFD_RELOC_SPARC_HH22 : BFD_RELOC_NONE); 1508 output_insn (insn, &the_insn); 1509 } 1510 1511 if (need_hi22_p) 1512 { 1513 the_insn.opcode = (SETHI_INSN | RD (dstreg) 1514 | (((need_xor10_p ? ~lower32 : lower32) 1515 >> 10) & 0x3fffff)); 1516 the_insn.reloc = (the_insn.exp.X_op != O_constant 1517 ? BFD_RELOC_SPARC_LM22 : BFD_RELOC_NONE); 1518 output_insn (insn, &the_insn); 1519 } 1520 1521 if (need_hm10_p) 1522 { 1523 the_insn.opcode = (OR_INSN 1524 | (need_hh22_p ? RS1 (upper_dstreg) : 0) 1525 | RD (upper_dstreg) 1526 | IMMED 1527 | (upper32 & (need_hh22_p ? 0x3ff : 0x1fff))); 1528 the_insn.reloc = (the_insn.exp.X_op != O_constant 1529 ? BFD_RELOC_SPARC_HM10 : BFD_RELOC_NONE); 1530 output_insn (insn, &the_insn); 1531 } 1532 1533 if (need_lo10_p) 1534 { 1535 /* FIXME: One nice optimization to do here is to OR the low part 1536 with the highpart if hi22 isn't needed and the low part is 1537 positive. */ 1538 the_insn.opcode = (OR_INSN | (need_hi22_p ? RS1 (dstreg) : 0) 1539 | RD (dstreg) 1540 | IMMED 1541 | (lower32 & (need_hi22_p ? 0x3ff : 0x1fff))); 1542 the_insn.reloc = (the_insn.exp.X_op != O_constant 1543 ? BFD_RELOC_LO10 : BFD_RELOC_NONE); 1544 output_insn (insn, &the_insn); 1545 } 1546 1547 /* If we needed to build the upper part, shift it into place. */ 1548 if (need_hh22_p || need_hm10_p) 1549 { 1550 the_insn.opcode = (SLLX_INSN | RS1 (upper_dstreg) | RD (upper_dstreg) 1551 | IMMED | 32); 1552 the_insn.reloc = BFD_RELOC_NONE; 1553 output_insn (insn, &the_insn); 1554 } 1555 1556 /* To get -1 in upper32, we do sethi %hi(~x), r; xor r, -0x400 | x, r. */ 1557 if (need_xor10_p) 1558 { 1559 the_insn.opcode = (XOR_INSN | RS1 (dstreg) | RD (dstreg) | IMMED 1560 | 0x1c00 | (lower32 & 0x3ff)); 1561 the_insn.reloc = BFD_RELOC_NONE; 1562 output_insn (insn, &the_insn); 1563 } 1564 1565 /* If we needed to build both upper and lower parts, OR them together. */ 1566 else if ((need_hh22_p || need_hm10_p) && (need_hi22_p || need_lo10_p)) 1567 { 1568 the_insn.opcode = (OR_INSN | RS1 (dstreg) | RS2 (upper_dstreg) 1569 | RD (dstreg)); 1570 the_insn.reloc = BFD_RELOC_NONE; 1571 output_insn (insn, &the_insn); 1572 } 1573 } 1574 1575 /* Main entry point to assemble one instruction. */ 1577 1578 void 1579 md_assemble (char *str) 1580 { 1581 const struct sparc_opcode *insn; 1582 int special_case; 1583 1584 know (str); 1585 special_case = sparc_ip (str, &insn); 1586 if (insn == NULL) 1587 return; 1588 1589 /* We warn about attempts to put a floating point branch in a delay slot, 1590 unless the delay slot has been annulled. */ 1591 if (last_insn != NULL 1592 && (insn->flags & F_FBR) != 0 1593 && (last_insn->flags & F_DELAYED) != 0 1594 /* ??? This test isn't completely accurate. We assume anything with 1595 F_{UNBR,CONDBR,FBR} set is annullable. */ 1596 && ((last_insn->flags & (F_UNBR | F_CONDBR | F_FBR)) == 0 1597 || (last_opcode & ANNUL) == 0)) 1598 as_warn (_("FP branch in delay slot")); 1599 1600 /* SPARC before v9 requires a nop instruction between a floating 1601 point instruction and a floating point branch. We insert one 1602 automatically, with a warning. */ 1603 if (max_architecture < SPARC_OPCODE_ARCH_V9 1604 && last_insn != NULL 1605 && (insn->flags & F_FBR) != 0 1606 && (last_insn->flags & F_FLOAT) != 0) 1607 { 1608 struct sparc_it nop_insn; 1609 1610 nop_insn.opcode = NOP_INSN; 1611 nop_insn.reloc = BFD_RELOC_NONE; 1612 output_insn (insn, &nop_insn); 1613 as_warn (_("FP branch preceded by FP instruction; NOP inserted")); 1614 } 1615 1616 switch (special_case) 1617 { 1618 case SPECIAL_CASE_NONE: 1619 /* Normal insn. */ 1620 output_insn (insn, &the_insn); 1621 break; 1622 1623 case SPECIAL_CASE_SETSW: 1624 synthetize_setsw (insn); 1625 break; 1626 1627 case SPECIAL_CASE_SET: 1628 synthetize_setuw (insn); 1629 break; 1630 1631 case SPECIAL_CASE_SETX: 1632 synthetize_setx (insn); 1633 break; 1634 1635 case SPECIAL_CASE_FDIV: 1636 { 1637 int rd = (the_insn.opcode >> 25) & 0x1f; 1638 1639 output_insn (insn, &the_insn); 1640 1641 /* According to information leaked from Sun, the "fdiv" instructions 1642 on early SPARC machines would produce incorrect results sometimes. 1643 The workaround is to add an fmovs of the destination register to 1644 itself just after the instruction. This was true on machines 1645 with Weitek 1165 float chips, such as the Sun-4/260 and /280. */ 1646 gas_assert (the_insn.reloc == BFD_RELOC_NONE); 1647 the_insn.opcode = FMOVS_INSN | rd | RD (rd); 1648 output_insn (insn, &the_insn); 1649 return; 1650 } 1651 1652 default: 1653 as_fatal (_("failed special case insn sanity check")); 1654 } 1655 } 1656 1657 static const char * 1658 get_hwcap_name (bfd_uint64_t mask) 1659 { 1660 if (mask & HWCAP_MUL32) 1661 return "mul32"; 1662 if (mask & HWCAP_DIV32) 1663 return "div32"; 1664 if (mask & HWCAP_FSMULD) 1665 return "fsmuld"; 1666 if (mask & HWCAP_V8PLUS) 1667 return "v8plus"; 1668 if (mask & HWCAP_POPC) 1669 return "popc"; 1670 if (mask & HWCAP_VIS) 1671 return "vis"; 1672 if (mask & HWCAP_VIS2) 1673 return "vis2"; 1674 if (mask & HWCAP_ASI_BLK_INIT) 1675 return "ASIBlkInit"; 1676 if (mask & HWCAP_FMAF) 1677 return "fmaf"; 1678 if (mask & HWCAP_VIS3) 1679 return "vis3"; 1680 if (mask & HWCAP_HPC) 1681 return "hpc"; 1682 if (mask & HWCAP_RANDOM) 1683 return "random"; 1684 if (mask & HWCAP_TRANS) 1685 return "trans"; 1686 if (mask & HWCAP_FJFMAU) 1687 return "fjfmau"; 1688 if (mask & HWCAP_IMA) 1689 return "ima"; 1690 if (mask & HWCAP_ASI_CACHE_SPARING) 1691 return "cspare"; 1692 if (mask & HWCAP_AES) 1693 return "aes"; 1694 if (mask & HWCAP_DES) 1695 return "des"; 1696 if (mask & HWCAP_KASUMI) 1697 return "kasumi"; 1698 if (mask & HWCAP_CAMELLIA) 1699 return "camellia"; 1700 if (mask & HWCAP_MD5) 1701 return "md5"; 1702 if (mask & HWCAP_SHA1) 1703 return "sha1"; 1704 if (mask & HWCAP_SHA256) 1705 return "sha256"; 1706 if (mask & HWCAP_SHA512) 1707 return "sha512"; 1708 if (mask & HWCAP_MPMUL) 1709 return "mpmul"; 1710 if (mask & HWCAP_MONT) 1711 return "mont"; 1712 if (mask & HWCAP_PAUSE) 1713 return "pause"; 1714 if (mask & HWCAP_CBCOND) 1715 return "cbcond"; 1716 if (mask & HWCAP_CRC32C) 1717 return "crc32c"; 1718 1719 mask = mask >> 32; 1720 if (mask & HWCAP2_FJATHPLUS) 1721 return "fjathplus"; 1722 if (mask & HWCAP2_VIS3B) 1723 return "vis3b"; 1724 if (mask & HWCAP2_ADP) 1725 return "adp"; 1726 if (mask & HWCAP2_SPARC5) 1727 return "sparc5"; 1728 if (mask & HWCAP2_MWAIT) 1729 return "mwait"; 1730 if (mask & HWCAP2_XMPMUL) 1731 return "xmpmul"; 1732 if (mask & HWCAP2_XMONT) 1733 return "xmont"; 1734 if (mask & HWCAP2_NSEC) 1735 return "nsec"; 1736 1737 return "UNKNOWN"; 1738 } 1739 1740 /* Subroutine of md_assemble to do the actual parsing. */ 1741 1742 static int 1743 sparc_ip (char *str, const struct sparc_opcode **pinsn) 1744 { 1745 const char *error_message = ""; 1746 char *s; 1747 const char *args; 1748 char c; 1749 const struct sparc_opcode *insn; 1750 char *argsStart; 1751 unsigned long opcode; 1752 unsigned int mask = 0; 1753 int match = 0; 1754 int comma = 0; 1755 int v9_arg_p; 1756 int special_case = SPECIAL_CASE_NONE; 1757 1758 s = str; 1759 if (ISLOWER (*s)) 1760 { 1761 do 1762 ++s; 1763 while (ISLOWER (*s) || ISDIGIT (*s) || *s == '_'); 1764 } 1765 1766 switch (*s) 1767 { 1768 case '\0': 1769 break; 1770 1771 case ',': 1772 comma = 1; 1773 /* Fall through. */ 1774 1775 case ' ': 1776 *s++ = '\0'; 1777 break; 1778 1779 default: 1780 as_bad (_("Unknown opcode: `%s'"), str); 1781 *pinsn = NULL; 1782 return special_case; 1783 } 1784 insn = (struct sparc_opcode *) hash_find (op_hash, str); 1785 *pinsn = insn; 1786 if (insn == NULL) 1787 { 1788 as_bad (_("Unknown opcode: `%s'"), str); 1789 return special_case; 1790 } 1791 if (comma) 1792 { 1793 *--s = ','; 1794 } 1795 1796 argsStart = s; 1797 for (;;) 1798 { 1799 opcode = insn->match; 1800 memset (&the_insn, '\0', sizeof (the_insn)); 1801 the_insn.reloc = BFD_RELOC_NONE; 1802 v9_arg_p = 0; 1803 1804 /* Build the opcode, checking as we go to make sure that the 1805 operands match. */ 1806 for (args = insn->args;; ++args) 1807 { 1808 switch (*args) 1809 { 1810 case 'K': 1811 { 1812 int kmask = 0; 1813 1814 /* Parse a series of masks. */ 1815 if (*s == '#') 1816 { 1817 while (*s == '#') 1818 { 1819 int jmask; 1820 1821 if (! parse_keyword_arg (sparc_encode_membar, &s, 1822 &jmask)) 1823 { 1824 error_message = _(": invalid membar mask name"); 1825 goto error; 1826 } 1827 kmask |= jmask; 1828 while (*s == ' ') 1829 ++s; 1830 if (*s == '|' || *s == '+') 1831 ++s; 1832 while (*s == ' ') 1833 ++s; 1834 } 1835 } 1836 else 1837 { 1838 if (! parse_const_expr_arg (&s, &kmask)) 1839 { 1840 error_message = _(": invalid membar mask expression"); 1841 goto error; 1842 } 1843 if (kmask < 0 || kmask > 127) 1844 { 1845 error_message = _(": invalid membar mask number"); 1846 goto error; 1847 } 1848 } 1849 1850 opcode |= MEMBAR (kmask); 1851 continue; 1852 } 1853 1854 case '3': 1855 { 1856 int smask = 0; 1857 1858 if (! parse_const_expr_arg (&s, &smask)) 1859 { 1860 error_message = _(": invalid siam mode expression"); 1861 goto error; 1862 } 1863 if (smask < 0 || smask > 7) 1864 { 1865 error_message = _(": invalid siam mode number"); 1866 goto error; 1867 } 1868 opcode |= smask; 1869 continue; 1870 } 1871 1872 case '*': 1873 { 1874 int fcn = 0; 1875 1876 /* Parse a prefetch function. */ 1877 if (*s == '#') 1878 { 1879 if (! parse_keyword_arg (sparc_encode_prefetch, &s, &fcn)) 1880 { 1881 error_message = _(": invalid prefetch function name"); 1882 goto error; 1883 } 1884 } 1885 else 1886 { 1887 if (! parse_const_expr_arg (&s, &fcn)) 1888 { 1889 error_message = _(": invalid prefetch function expression"); 1890 goto error; 1891 } 1892 if (fcn < 0 || fcn > 31) 1893 { 1894 error_message = _(": invalid prefetch function number"); 1895 goto error; 1896 } 1897 } 1898 opcode |= RD (fcn); 1899 continue; 1900 } 1901 1902 case '!': 1903 case '?': 1904 /* Parse a sparc64 privileged register. */ 1905 if (*s == '%') 1906 { 1907 struct priv_reg_entry *p; 1908 unsigned int len = 9999999; /* Init to make gcc happy. */ 1909 1910 s += 1; 1911 for (p = priv_reg_table; p->name; p++) 1912 if (p->name[0] == s[0]) 1913 { 1914 len = strlen (p->name); 1915 if (strncmp (p->name, s, len) == 0) 1916 break; 1917 } 1918 1919 if (!p->name) 1920 { 1921 error_message = _(": unrecognizable privileged register"); 1922 goto error; 1923 } 1924 1925 if (((opcode >> (*args == '?' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1926 { 1927 error_message = _(": unrecognizable privileged register"); 1928 goto error; 1929 } 1930 1931 s += len; 1932 continue; 1933 } 1934 else 1935 { 1936 error_message = _(": unrecognizable privileged register"); 1937 goto error; 1938 } 1939 1940 case '$': 1941 case '%': 1942 /* Parse a sparc64 hyperprivileged register. */ 1943 if (*s == '%') 1944 { 1945 struct priv_reg_entry *p; 1946 unsigned int len = 9999999; /* Init to make gcc happy. */ 1947 1948 s += 1; 1949 for (p = hpriv_reg_table; p->name; p++) 1950 if (p->name[0] == s[0]) 1951 { 1952 len = strlen (p->name); 1953 if (strncmp (p->name, s, len) == 0) 1954 break; 1955 } 1956 1957 if (!p->name) 1958 { 1959 error_message = _(": unrecognizable hyperprivileged register"); 1960 goto error; 1961 } 1962 1963 if (((opcode >> (*args == '$' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 1964 { 1965 error_message = _(": unrecognizable hyperprivileged register"); 1966 goto error; 1967 } 1968 1969 s += len; 1970 continue; 1971 } 1972 else 1973 { 1974 error_message = _(": unrecognizable hyperprivileged register"); 1975 goto error; 1976 } 1977 1978 case '_': 1979 case '/': 1980 /* Parse a v9a or later ancillary state register. */ 1981 if (*s == '%') 1982 { 1983 struct priv_reg_entry *p; 1984 unsigned int len = 9999999; /* Init to make gcc happy. */ 1985 1986 s += 1; 1987 for (p = v9a_asr_table; p->name; p++) 1988 if (p->name[0] == s[0]) 1989 { 1990 len = strlen (p->name); 1991 if (strncmp (p->name, s, len) == 0) 1992 break; 1993 } 1994 1995 if (!p->name) 1996 { 1997 error_message = _(": unrecognizable ancillary state register"); 1998 goto error; 1999 } 2000 2001 if (((opcode >> (*args == '/' ? 14 : 25)) & 0x1f) != (unsigned) p->regnum) 2002 { 2003 error_message = _(": unrecognizable ancillary state register"); 2004 goto error; 2005 } 2006 2007 s += len; 2008 continue; 2009 } 2010 else 2011 { 2012 error_message = _(": unrecognizable ancillary state register"); 2013 goto error; 2014 } 2015 2016 case 'M': 2017 case 'm': 2018 if (strncmp (s, "%asr", 4) == 0) 2019 { 2020 s += 4; 2021 2022 if (ISDIGIT (*s)) 2023 { 2024 long num = 0; 2025 2026 while (ISDIGIT (*s)) 2027 { 2028 num = num * 10 + *s - '0'; 2029 ++s; 2030 } 2031 2032 /* We used to check here for the asr number to 2033 be between 16 and 31 in V9 and later, as 2034 mandated by the section C.1.1 "Register 2035 Names" in the SPARC spec. However, we 2036 decided to remove this restriction as a) it 2037 introduces problems when new V9 asr registers 2038 are introduced, b) the Solaris assembler 2039 doesn't implement this restriction and c) the 2040 restriction will go away in future revisions 2041 of the Oracle SPARC Architecture. */ 2042 2043 if (num < 0 || 31 < num) 2044 { 2045 error_message = _(": asr number must be between 0 and 31"); 2046 goto error; 2047 } 2048 2049 opcode |= (*args == 'M' ? RS1 (num) : RD (num)); 2050 continue; 2051 } 2052 else 2053 { 2054 error_message = _(": expecting %asrN"); 2055 goto error; 2056 } 2057 } /* if %asr */ 2058 break; 2059 2060 case 'I': 2061 the_insn.reloc = BFD_RELOC_SPARC_11; 2062 goto immediate; 2063 2064 case 'j': 2065 the_insn.reloc = BFD_RELOC_SPARC_10; 2066 goto immediate; 2067 2068 case ')': 2069 if (*s == ' ') 2070 s++; 2071 if ((s[0] == '0' && s[1] == 'x' && ISXDIGIT (s[2])) 2072 || ISDIGIT (*s)) 2073 { 2074 long num = 0; 2075 2076 if (s[0] == '0' && s[1] == 'x') 2077 { 2078 s += 2; 2079 while (ISXDIGIT (*s)) 2080 { 2081 num <<= 4; 2082 num |= hex_value (*s); 2083 ++s; 2084 } 2085 } 2086 else 2087 { 2088 while (ISDIGIT (*s)) 2089 { 2090 num = num * 10 + *s - '0'; 2091 ++s; 2092 } 2093 } 2094 if (num < 0 || num > 31) 2095 { 2096 error_message = _(": crypto immediate must be between 0 and 31"); 2097 goto error; 2098 } 2099 2100 opcode |= RS3 (num); 2101 continue; 2102 } 2103 else 2104 { 2105 error_message = _(": expecting crypto immediate"); 2106 goto error; 2107 } 2108 2109 case 'X': 2110 /* V8 systems don't understand BFD_RELOC_SPARC_5. */ 2111 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2112 the_insn.reloc = BFD_RELOC_SPARC_5; 2113 else 2114 the_insn.reloc = BFD_RELOC_SPARC13; 2115 /* These fields are unsigned, but for upward compatibility, 2116 allow negative values as well. */ 2117 goto immediate; 2118 2119 case 'Y': 2120 /* V8 systems don't understand BFD_RELOC_SPARC_6. */ 2121 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2122 the_insn.reloc = BFD_RELOC_SPARC_6; 2123 else 2124 the_insn.reloc = BFD_RELOC_SPARC13; 2125 /* These fields are unsigned, but for upward compatibility, 2126 allow negative values as well. */ 2127 goto immediate; 2128 2129 case 'k': 2130 the_insn.reloc = /* RELOC_WDISP2_14 */ BFD_RELOC_SPARC_WDISP16; 2131 the_insn.pcrel = 1; 2132 goto immediate; 2133 2134 case '=': 2135 the_insn.reloc = /* RELOC_WDISP2_8 */ BFD_RELOC_SPARC_WDISP10; 2136 the_insn.pcrel = 1; 2137 goto immediate; 2138 2139 case 'G': 2140 the_insn.reloc = BFD_RELOC_SPARC_WDISP19; 2141 the_insn.pcrel = 1; 2142 goto immediate; 2143 2144 case 'N': 2145 if (*s == 'p' && s[1] == 'n') 2146 { 2147 s += 2; 2148 continue; 2149 } 2150 break; 2151 2152 case 'T': 2153 if (*s == 'p' && s[1] == 't') 2154 { 2155 s += 2; 2156 continue; 2157 } 2158 break; 2159 2160 case 'z': 2161 if (*s == ' ') 2162 { 2163 ++s; 2164 } 2165 if ((strncmp (s, "%icc", 4) == 0) 2166 || (sparc_arch_size == 32 && strncmp (s, "%ncc", 4) == 0)) 2167 { 2168 s += 4; 2169 continue; 2170 } 2171 break; 2172 2173 case 'Z': 2174 if (*s == ' ') 2175 { 2176 ++s; 2177 } 2178 if ((strncmp (s, "%xcc", 4) == 0) 2179 || (sparc_arch_size == 64 && strncmp (s, "%ncc", 4) == 0)) 2180 { 2181 s += 4; 2182 continue; 2183 } 2184 break; 2185 2186 case '6': 2187 if (*s == ' ') 2188 { 2189 ++s; 2190 } 2191 if (strncmp (s, "%fcc0", 5) == 0) 2192 { 2193 s += 5; 2194 continue; 2195 } 2196 break; 2197 2198 case '7': 2199 if (*s == ' ') 2200 { 2201 ++s; 2202 } 2203 if (strncmp (s, "%fcc1", 5) == 0) 2204 { 2205 s += 5; 2206 continue; 2207 } 2208 break; 2209 2210 case '8': 2211 if (*s == ' ') 2212 { 2213 ++s; 2214 } 2215 if (strncmp (s, "%fcc2", 5) == 0) 2216 { 2217 s += 5; 2218 continue; 2219 } 2220 break; 2221 2222 case '9': 2223 if (*s == ' ') 2224 { 2225 ++s; 2226 } 2227 if (strncmp (s, "%fcc3", 5) == 0) 2228 { 2229 s += 5; 2230 continue; 2231 } 2232 break; 2233 2234 case 'P': 2235 if (strncmp (s, "%pc", 3) == 0) 2236 { 2237 s += 3; 2238 continue; 2239 } 2240 break; 2241 2242 case 'W': 2243 if (strncmp (s, "%tick", 5) == 0) 2244 { 2245 s += 5; 2246 continue; 2247 } 2248 break; 2249 2250 case '\0': /* End of args. */ 2251 if (s[0] == ',' && s[1] == '%') 2252 { 2253 char *s1; 2254 int npar = 0; 2255 const struct perc_entry *p; 2256 2257 for (p = perc_table; p->type != perc_entry_none; p++) 2258 if ((p->type == perc_entry_post_pop || p->type == perc_entry_reg) 2259 && strncmp (s + 2, p->name, p->len) == 0) 2260 break; 2261 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2262 break; 2263 2264 if (s[p->len + 2] != '(') 2265 { 2266 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2267 return special_case; 2268 } 2269 2270 if (! (p->pop->flags & F_POP_TLS_CALL) 2271 && the_insn.reloc != BFD_RELOC_NONE) 2272 { 2273 as_bad (_("Illegal operands: %%%s cannot be used together with other relocs in the insn ()"), 2274 p->name); 2275 return special_case; 2276 } 2277 2278 if ((p->pop->flags & F_POP_TLS_CALL) 2279 && (the_insn.reloc != BFD_RELOC_32_PCREL_S2 2280 || the_insn.exp.X_add_number != 0 2281 || the_insn.exp.X_add_symbol 2282 != symbol_find_or_make ("__tls_get_addr"))) 2283 { 2284 as_bad (_("Illegal operands: %%%s can be only used with call __tls_get_addr"), 2285 p->name); 2286 return special_case; 2287 } 2288 2289 the_insn.reloc = p->pop->reloc; 2290 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2291 s += p->len + 3; 2292 2293 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2294 if (*s1 == '(') 2295 npar++; 2296 else if (*s1 == ')') 2297 { 2298 if (!npar) 2299 break; 2300 npar--; 2301 } 2302 2303 if (*s1 != ')') 2304 { 2305 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2306 return special_case; 2307 } 2308 2309 *s1 = '\0'; 2310 (void) get_expression (s); 2311 *s1 = ')'; 2312 s = s1 + 1; 2313 } 2314 if (*s == '\0') 2315 match = 1; 2316 break; 2317 2318 case '+': 2319 if (*s == '+') 2320 { 2321 ++s; 2322 continue; 2323 } 2324 if (*s == '-') 2325 { 2326 continue; 2327 } 2328 break; 2329 2330 case '[': /* These must match exactly. */ 2331 case ']': 2332 case ',': 2333 case ' ': 2334 if (*s++ == *args) 2335 continue; 2336 break; 2337 2338 case '#': /* Must be at least one digit. */ 2339 if (ISDIGIT (*s++)) 2340 { 2341 while (ISDIGIT (*s)) 2342 { 2343 ++s; 2344 } 2345 continue; 2346 } 2347 break; 2348 2349 case 'C': /* Coprocessor state register. */ 2350 if (strncmp (s, "%csr", 4) == 0) 2351 { 2352 s += 4; 2353 continue; 2354 } 2355 break; 2356 2357 case 'b': /* Next operand is a coprocessor register. */ 2358 case 'c': 2359 case 'D': 2360 if (*s++ == '%' && *s++ == 'c' && ISDIGIT (*s)) 2361 { 2362 mask = *s++; 2363 if (ISDIGIT (*s)) 2364 { 2365 mask = 10 * (mask - '0') + (*s++ - '0'); 2366 if (mask >= 32) 2367 { 2368 break; 2369 } 2370 } 2371 else 2372 { 2373 mask -= '0'; 2374 } 2375 switch (*args) 2376 { 2377 2378 case 'b': 2379 opcode |= mask << 14; 2380 continue; 2381 2382 case 'c': 2383 opcode |= mask; 2384 continue; 2385 2386 case 'D': 2387 opcode |= mask << 25; 2388 continue; 2389 } 2390 } 2391 break; 2392 2393 case 'r': /* next operand must be a register */ 2394 case 'O': 2395 case '1': 2396 case '2': 2397 case 'd': 2398 if (*s++ == '%') 2399 { 2400 switch (c = *s++) 2401 { 2402 2403 case 'f': /* frame pointer */ 2404 if (*s++ == 'p') 2405 { 2406 mask = 0x1e; 2407 break; 2408 } 2409 goto error; 2410 2411 case 'g': /* global register */ 2412 c = *s++; 2413 if (isoctal (c)) 2414 { 2415 mask = c - '0'; 2416 break; 2417 } 2418 goto error; 2419 2420 case 'i': /* in register */ 2421 c = *s++; 2422 if (isoctal (c)) 2423 { 2424 mask = c - '0' + 24; 2425 break; 2426 } 2427 goto error; 2428 2429 case 'l': /* local register */ 2430 c = *s++; 2431 if (isoctal (c)) 2432 { 2433 mask = (c - '0' + 16); 2434 break; 2435 } 2436 goto error; 2437 2438 case 'o': /* out register */ 2439 c = *s++; 2440 if (isoctal (c)) 2441 { 2442 mask = (c - '0' + 8); 2443 break; 2444 } 2445 goto error; 2446 2447 case 's': /* stack pointer */ 2448 if (*s++ == 'p') 2449 { 2450 mask = 0xe; 2451 break; 2452 } 2453 goto error; 2454 2455 case 'r': /* any register */ 2456 if (!ISDIGIT ((c = *s++))) 2457 { 2458 goto error; 2459 } 2460 /* FALLTHROUGH */ 2461 case '0': 2462 case '1': 2463 case '2': 2464 case '3': 2465 case '4': 2466 case '5': 2467 case '6': 2468 case '7': 2469 case '8': 2470 case '9': 2471 if (ISDIGIT (*s)) 2472 { 2473 if ((c = 10 * (c - '0') + (*s++ - '0')) >= 32) 2474 { 2475 goto error; 2476 } 2477 } 2478 else 2479 { 2480 c -= '0'; 2481 } 2482 mask = c; 2483 break; 2484 2485 default: 2486 goto error; 2487 } 2488 2489 if ((mask & ~1) == 2 && sparc_arch_size == 64 2490 && no_undeclared_regs && ! globals[mask]) 2491 as_bad (_("detected global register use not covered by .register pseudo-op")); 2492 2493 /* Got the register, now figure out where 2494 it goes in the opcode. */ 2495 switch (*args) 2496 { 2497 case '1': 2498 opcode |= mask << 14; 2499 continue; 2500 2501 case '2': 2502 opcode |= mask; 2503 continue; 2504 2505 case 'd': 2506 opcode |= mask << 25; 2507 continue; 2508 2509 case 'r': 2510 opcode |= (mask << 25) | (mask << 14); 2511 continue; 2512 2513 case 'O': 2514 opcode |= (mask << 25) | (mask << 0); 2515 continue; 2516 } 2517 } 2518 break; 2519 2520 case 'e': /* next operand is a floating point register */ 2521 case 'v': 2522 case 'V': 2523 2524 case 'f': 2525 case 'B': 2526 case 'R': 2527 2528 case '4': 2529 case '5': 2530 2531 case 'g': 2532 case 'H': 2533 case 'J': 2534 case '}': 2535 { 2536 char format; 2537 2538 if (*s++ == '%' 2539 && ((format = *s) == 'f' 2540 || format == 'd' 2541 || format == 'q') 2542 && ISDIGIT (*++s)) 2543 { 2544 for (mask = 0; ISDIGIT (*s); ++s) 2545 { 2546 mask = 10 * mask + (*s - '0'); 2547 } /* read the number */ 2548 2549 if ((*args == 'v' 2550 || *args == 'B' 2551 || *args == '5' 2552 || *args == 'H' 2553 || format == 'd') 2554 && (mask & 1)) 2555 { 2556 /* register must be even numbered */ 2557 break; 2558 } 2559 2560 if ((*args == 'V' 2561 || *args == 'R' 2562 || *args == 'J' 2563 || format == 'q') 2564 && (mask & 3)) 2565 { 2566 /* register must be multiple of 4 */ 2567 break; 2568 } 2569 2570 if (mask >= 64) 2571 { 2572 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2573 error_message = _(": There are only 64 f registers; [0-63]"); 2574 else 2575 error_message = _(": There are only 32 f registers; [0-31]"); 2576 goto error; 2577 } /* on error */ 2578 else if (mask >= 32) 2579 { 2580 if (SPARC_OPCODE_ARCH_V9_P (max_architecture)) 2581 { 2582 if (*args == 'e' || *args == 'f' || *args == 'g') 2583 { 2584 error_message 2585 = _(": There are only 32 single precision f registers; [0-31]"); 2586 goto error; 2587 } 2588 v9_arg_p = 1; 2589 mask -= 31; /* wrap high bit */ 2590 } 2591 else 2592 { 2593 error_message = _(": There are only 32 f registers; [0-31]"); 2594 goto error; 2595 } 2596 } 2597 } 2598 else 2599 { 2600 break; 2601 } /* if not an 'f' register. */ 2602 2603 if (*args == '}' && mask != RS2 (opcode)) 2604 { 2605 error_message 2606 = _(": Instruction requires frs2 and frsd must be the same register"); 2607 goto error; 2608 } 2609 2610 switch (*args) 2611 { 2612 case 'v': 2613 case 'V': 2614 case 'e': 2615 opcode |= RS1 (mask); 2616 continue; 2617 2618 case 'f': 2619 case 'B': 2620 case 'R': 2621 opcode |= RS2 (mask); 2622 continue; 2623 2624 case '4': 2625 case '5': 2626 opcode |= RS3 (mask); 2627 continue; 2628 2629 case 'g': 2630 case 'H': 2631 case 'J': 2632 case '}': 2633 opcode |= RD (mask); 2634 continue; 2635 } /* Pack it in. */ 2636 2637 know (0); 2638 break; 2639 } /* float arg */ 2640 2641 case 'F': 2642 if (strncmp (s, "%fsr", 4) == 0) 2643 { 2644 s += 4; 2645 continue; 2646 } 2647 break; 2648 2649 case '(': 2650 if (strncmp (s, "%efsr", 5) == 0) 2651 { 2652 s += 5; 2653 continue; 2654 } 2655 break; 2656 2657 case '0': /* 64 bit immediate (set, setsw, setx insn) */ 2658 the_insn.reloc = BFD_RELOC_NONE; /* reloc handled elsewhere */ 2659 goto immediate; 2660 2661 case 'l': /* 22 bit PC relative immediate */ 2662 the_insn.reloc = BFD_RELOC_SPARC_WDISP22; 2663 the_insn.pcrel = 1; 2664 goto immediate; 2665 2666 case 'L': /* 30 bit immediate */ 2667 the_insn.reloc = BFD_RELOC_32_PCREL_S2; 2668 the_insn.pcrel = 1; 2669 goto immediate; 2670 2671 case 'h': 2672 case 'n': /* 22 bit immediate */ 2673 the_insn.reloc = BFD_RELOC_SPARC22; 2674 goto immediate; 2675 2676 case 'i': /* 13 bit immediate */ 2677 the_insn.reloc = BFD_RELOC_SPARC13; 2678 2679 /* fallthrough */ 2680 2681 immediate: 2682 if (*s == ' ') 2683 s++; 2684 2685 { 2686 char *s1; 2687 const char *op_arg = NULL; 2688 static expressionS op_exp; 2689 bfd_reloc_code_real_type old_reloc = the_insn.reloc; 2690 2691 /* Check for %hi, etc. */ 2692 if (*s == '%') 2693 { 2694 const struct perc_entry *p; 2695 2696 for (p = perc_table; p->type != perc_entry_none; p++) 2697 if ((p->type == perc_entry_imm_pop || p->type == perc_entry_reg) 2698 && strncmp (s + 1, p->name, p->len) == 0) 2699 break; 2700 if (p->type == perc_entry_none || p->type == perc_entry_reg) 2701 break; 2702 2703 if (s[p->len + 1] != '(') 2704 { 2705 as_bad (_("Illegal operands: %%%s requires arguments in ()"), p->name); 2706 return special_case; 2707 } 2708 2709 op_arg = p->name; 2710 the_insn.reloc = p->pop->reloc; 2711 s += p->len + 2; 2712 v9_arg_p = p->pop->flags & F_POP_V9; 2713 } 2714 2715 /* Note that if the get_expression() fails, we will still 2716 have created U entries in the symbol table for the 2717 'symbols' in the input string. Try not to create U 2718 symbols for registers, etc. */ 2719 2720 /* This stuff checks to see if the expression ends in 2721 +%reg. If it does, it removes the register from 2722 the expression, and re-sets 's' to point to the 2723 right place. */ 2724 2725 if (op_arg) 2726 { 2727 int npar = 0; 2728 2729 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2730 if (*s1 == '(') 2731 npar++; 2732 else if (*s1 == ')') 2733 { 2734 if (!npar) 2735 break; 2736 npar--; 2737 } 2738 2739 if (*s1 != ')') 2740 { 2741 as_bad (_("Illegal operands: %%%s requires arguments in ()"), op_arg); 2742 return special_case; 2743 } 2744 2745 *s1 = '\0'; 2746 (void) get_expression (s); 2747 *s1 = ')'; 2748 if (expr_end != s1) 2749 { 2750 as_bad (_("Expression inside %%%s could not be parsed"), op_arg); 2751 return special_case; 2752 } 2753 s = s1 + 1; 2754 if (*s == ',' || *s == ']' || !*s) 2755 continue; 2756 if (*s != '+' && *s != '-') 2757 { 2758 as_bad (_("Illegal operands: Can't do arithmetics other than + and - involving %%%s()"), op_arg); 2759 return special_case; 2760 } 2761 *s1 = '0'; 2762 s = s1; 2763 op_exp = the_insn.exp; 2764 memset (&the_insn.exp, 0, sizeof (the_insn.exp)); 2765 } 2766 2767 for (s1 = s; *s1 && *s1 != ',' && *s1 != ']'; s1++) 2768 ; 2769 2770 if (s1 != s && ISDIGIT (s1[-1])) 2771 { 2772 if (s1[-2] == '%' && s1[-3] == '+') 2773 s1 -= 3; 2774 else if (strchr ("golir0123456789", s1[-2]) && s1[-3] == '%' && s1[-4] == '+') 2775 s1 -= 4; 2776 else if (s1[-3] == 'r' && s1[-4] == '%' && s1[-5] == '+') 2777 s1 -= 5; 2778 else 2779 s1 = NULL; 2780 if (s1) 2781 { 2782 *s1 = '\0'; 2783 if (op_arg && s1 == s + 1) 2784 the_insn.exp.X_op = O_absent; 2785 else 2786 (void) get_expression (s); 2787 *s1 = '+'; 2788 if (op_arg) 2789 *s = ')'; 2790 s = s1; 2791 } 2792 } 2793 else 2794 s1 = NULL; 2795 2796 if (!s1) 2797 { 2798 (void) get_expression (s); 2799 if (op_arg) 2800 *s = ')'; 2801 s = expr_end; 2802 } 2803 2804 if (op_arg) 2805 { 2806 the_insn.exp2 = the_insn.exp; 2807 the_insn.exp = op_exp; 2808 if (the_insn.exp2.X_op == O_absent) 2809 the_insn.exp2.X_op = O_illegal; 2810 else if (the_insn.exp.X_op == O_absent) 2811 { 2812 the_insn.exp = the_insn.exp2; 2813 the_insn.exp2.X_op = O_illegal; 2814 } 2815 else if (the_insn.exp.X_op == O_constant) 2816 { 2817 valueT val = the_insn.exp.X_add_number; 2818 switch (the_insn.reloc) 2819 { 2820 default: 2821 break; 2822 2823 case BFD_RELOC_SPARC_HH22: 2824 val = BSR (val, 32); 2825 /* Fall through. */ 2826 2827 case BFD_RELOC_SPARC_LM22: 2828 case BFD_RELOC_HI22: 2829 val = (val >> 10) & 0x3fffff; 2830 break; 2831 2832 case BFD_RELOC_SPARC_HM10: 2833 val = BSR (val, 32); 2834 /* Fall through. */ 2835 2836 case BFD_RELOC_LO10: 2837 val &= 0x3ff; 2838 break; 2839 2840 case BFD_RELOC_SPARC_H34: 2841 val >>= 12; 2842 val &= 0x3fffff; 2843 break; 2844 2845 case BFD_RELOC_SPARC_H44: 2846 val >>= 22; 2847 val &= 0x3fffff; 2848 break; 2849 2850 case BFD_RELOC_SPARC_M44: 2851 val >>= 12; 2852 val &= 0x3ff; 2853 break; 2854 2855 case BFD_RELOC_SPARC_L44: 2856 val &= 0xfff; 2857 break; 2858 2859 case BFD_RELOC_SPARC_HIX22: 2860 val = ~val; 2861 val = (val >> 10) & 0x3fffff; 2862 break; 2863 2864 case BFD_RELOC_SPARC_LOX10: 2865 val = (val & 0x3ff) | 0x1c00; 2866 break; 2867 } 2868 the_insn.exp = the_insn.exp2; 2869 the_insn.exp.X_add_number += val; 2870 the_insn.exp2.X_op = O_illegal; 2871 the_insn.reloc = old_reloc; 2872 } 2873 else if (the_insn.exp2.X_op != O_constant) 2874 { 2875 as_bad (_("Illegal operands: Can't add non-constant expression to %%%s()"), op_arg); 2876 return special_case; 2877 } 2878 else 2879 { 2880 if (old_reloc != BFD_RELOC_SPARC13 2881 || the_insn.reloc != BFD_RELOC_LO10 2882 || sparc_arch_size != 64 2883 || sparc_pic_code) 2884 { 2885 as_bad (_("Illegal operands: Can't do arithmetics involving %%%s() of a relocatable symbol"), op_arg); 2886 return special_case; 2887 } 2888 the_insn.reloc = BFD_RELOC_SPARC_OLO10; 2889 } 2890 } 2891 } 2892 /* Check for constants that don't require emitting a reloc. */ 2893 if (the_insn.exp.X_op == O_constant 2894 && the_insn.exp.X_add_symbol == 0 2895 && the_insn.exp.X_op_symbol == 0) 2896 { 2897 /* For pc-relative call instructions, we reject 2898 constants to get better code. */ 2899 if (the_insn.pcrel 2900 && the_insn.reloc == BFD_RELOC_32_PCREL_S2 2901 && in_signed_range (the_insn.exp.X_add_number, 0x3fff)) 2902 { 2903 error_message = _(": PC-relative operand can't be a constant"); 2904 goto error; 2905 } 2906 2907 if (the_insn.reloc >= BFD_RELOC_SPARC_TLS_GD_HI22 2908 && the_insn.reloc <= BFD_RELOC_SPARC_TLS_TPOFF64) 2909 { 2910 error_message = _(": TLS operand can't be a constant"); 2911 goto error; 2912 } 2913 2914 /* Constants that won't fit are checked in md_apply_fix 2915 and bfd_install_relocation. 2916 ??? It would be preferable to install the constants 2917 into the insn here and save having to create a fixS 2918 for each one. There already exists code to handle 2919 all the various cases (e.g. in md_apply_fix and 2920 bfd_install_relocation) so duplicating all that code 2921 here isn't right. */ 2922 2923 /* This is a special case to handle cbcond instructions 2924 properly, which can need two relocations. The first 2925 one is for the 5-bit immediate field and the latter 2926 is going to be for the WDISP10 branch part. We 2927 handle the R_SPARC_5 immediate directly here so that 2928 we don't need to add support for multiple relocations 2929 in one instruction just yet. */ 2930 if (the_insn.reloc == BFD_RELOC_SPARC_5) 2931 { 2932 valueT val = the_insn.exp.X_add_number; 2933 2934 if (! in_bitfield_range (val, 0x1f)) 2935 { 2936 error_message = _(": Immediate value in cbcond is out of range."); 2937 goto error; 2938 } 2939 opcode |= val & 0x1f; 2940 the_insn.reloc = BFD_RELOC_NONE; 2941 } 2942 } 2943 2944 continue; 2945 2946 case 'a': 2947 if (*s++ == 'a') 2948 { 2949 opcode |= ANNUL; 2950 continue; 2951 } 2952 break; 2953 2954 case 'A': 2955 { 2956 int asi = 0; 2957 2958 /* Parse an asi. */ 2959 if (*s == '#') 2960 { 2961 if (! parse_keyword_arg (sparc_encode_asi, &s, &asi)) 2962 { 2963 error_message = _(": invalid ASI name"); 2964 goto error; 2965 } 2966 } 2967 else 2968 { 2969 if (! parse_const_expr_arg (&s, &asi)) 2970 { 2971 error_message = _(": invalid ASI expression"); 2972 goto error; 2973 } 2974 if (asi < 0 || asi > 255) 2975 { 2976 error_message = _(": invalid ASI number"); 2977 goto error; 2978 } 2979 } 2980 opcode |= ASI (asi); 2981 continue; 2982 } /* Alternate space. */ 2983 2984 case 'p': 2985 if (strncmp (s, "%psr", 4) == 0) 2986 { 2987 s += 4; 2988 continue; 2989 } 2990 break; 2991 2992 case 'q': /* Floating point queue. */ 2993 if (strncmp (s, "%fq", 3) == 0) 2994 { 2995 s += 3; 2996 continue; 2997 } 2998 break; 2999 3000 case 'Q': /* Coprocessor queue. */ 3001 if (strncmp (s, "%cq", 3) == 0) 3002 { 3003 s += 3; 3004 continue; 3005 } 3006 break; 3007 3008 case 'S': 3009 if (strcmp (str, "set") == 0 3010 || strcmp (str, "setuw") == 0) 3011 { 3012 special_case = SPECIAL_CASE_SET; 3013 continue; 3014 } 3015 else if (strcmp (str, "setsw") == 0) 3016 { 3017 special_case = SPECIAL_CASE_SETSW; 3018 continue; 3019 } 3020 else if (strcmp (str, "setx") == 0) 3021 { 3022 special_case = SPECIAL_CASE_SETX; 3023 continue; 3024 } 3025 else if (strncmp (str, "fdiv", 4) == 0) 3026 { 3027 special_case = SPECIAL_CASE_FDIV; 3028 continue; 3029 } 3030 break; 3031 3032 case 'o': 3033 if (strncmp (s, "%asi", 4) != 0) 3034 break; 3035 s += 4; 3036 continue; 3037 3038 case 's': 3039 if (strncmp (s, "%fprs", 5) != 0) 3040 break; 3041 s += 5; 3042 continue; 3043 3044 case '{': 3045 if (strncmp (s, "%mcdper",7) != 0) 3046 break; 3047 s += 7; 3048 continue; 3049 3050 case 'E': 3051 if (strncmp (s, "%ccr", 4) != 0) 3052 break; 3053 s += 4; 3054 continue; 3055 3056 case 't': 3057 if (strncmp (s, "%tbr", 4) != 0) 3058 break; 3059 s += 4; 3060 continue; 3061 3062 case 'w': 3063 if (strncmp (s, "%wim", 4) != 0) 3064 break; 3065 s += 4; 3066 continue; 3067 3068 case 'x': 3069 { 3070 char *push = input_line_pointer; 3071 expressionS e; 3072 3073 input_line_pointer = s; 3074 expression (&e); 3075 if (e.X_op == O_constant) 3076 { 3077 int n = e.X_add_number; 3078 if (n != e.X_add_number || (n & ~0x1ff) != 0) 3079 as_bad (_("OPF immediate operand out of range (0-0x1ff)")); 3080 else 3081 opcode |= e.X_add_number << 5; 3082 } 3083 else 3084 as_bad (_("non-immediate OPF operand, ignored")); 3085 s = input_line_pointer; 3086 input_line_pointer = push; 3087 continue; 3088 } 3089 3090 case 'y': 3091 if (strncmp (s, "%y", 2) != 0) 3092 break; 3093 s += 2; 3094 continue; 3095 3096 case 'u': 3097 case 'U': 3098 { 3099 /* Parse a sparclet cpreg. */ 3100 int cpreg; 3101 if (! parse_keyword_arg (sparc_encode_sparclet_cpreg, &s, &cpreg)) 3102 { 3103 error_message = _(": invalid cpreg name"); 3104 goto error; 3105 } 3106 opcode |= (*args == 'U' ? RS1 (cpreg) : RD (cpreg)); 3107 continue; 3108 } 3109 3110 default: 3111 as_fatal (_("failed sanity check.")); 3112 } /* switch on arg code. */ 3113 3114 /* Break out of for() loop. */ 3115 break; 3116 } /* For each arg that we expect. */ 3117 3118 error: 3119 if (match == 0) 3120 { 3121 /* Args don't match. */ 3122 if (&insn[1] - sparc_opcodes < sparc_num_opcodes 3123 && (insn->name == insn[1].name 3124 || !strcmp (insn->name, insn[1].name))) 3125 { 3126 ++insn; 3127 s = argsStart; 3128 continue; 3129 } 3130 else 3131 { 3132 as_bad (_("Illegal operands%s"), error_message); 3133 return special_case; 3134 } 3135 } 3136 else 3137 { 3138 /* We have a match. Now see if the architecture is OK. */ 3139 int needed_arch_mask = insn->architecture; 3140 bfd_uint64_t hwcaps 3141 = (((bfd_uint64_t) insn->hwcaps2) << 32) | insn->hwcaps; 3142 3143 #if defined(OBJ_ELF) && !defined(TE_SOLARIS) 3144 if (hwcaps) 3145 hwcap_seen |= hwcaps; 3146 #endif 3147 if (v9_arg_p) 3148 { 3149 needed_arch_mask &= 3150 ~(SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9) - 1); 3151 if (! needed_arch_mask) 3152 needed_arch_mask = 3153 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9); 3154 } 3155 3156 if (needed_arch_mask 3157 & SPARC_OPCODE_SUPPORTED (current_architecture)) 3158 /* OK. */ 3159 ; 3160 /* Can we bump up the architecture? */ 3161 else if (needed_arch_mask 3162 & SPARC_OPCODE_SUPPORTED (max_architecture)) 3163 { 3164 enum sparc_opcode_arch_val needed_architecture = 3165 sparc_ffs (SPARC_OPCODE_SUPPORTED (max_architecture) 3166 & needed_arch_mask); 3167 3168 gas_assert (needed_architecture <= SPARC_OPCODE_ARCH_MAX); 3169 if (warn_on_bump 3170 && needed_architecture > warn_after_architecture) 3171 { 3172 as_warn (_("architecture bumped from \"%s\" to \"%s\" on \"%s\""), 3173 sparc_opcode_archs[current_architecture].name, 3174 sparc_opcode_archs[needed_architecture].name, 3175 str); 3176 warn_after_architecture = needed_architecture; 3177 } 3178 current_architecture = needed_architecture; 3179 hwcap_allowed |= hwcaps; 3180 } 3181 /* Conflict. */ 3182 /* ??? This seems to be a bit fragile. What if the next entry in 3183 the opcode table is the one we want and it is supported? 3184 It is possible to arrange the table today so that this can't 3185 happen but what about tomorrow? */ 3186 else 3187 { 3188 int arch, printed_one_p = 0; 3189 char *p; 3190 char required_archs[SPARC_OPCODE_ARCH_MAX * 16]; 3191 3192 /* Create a list of the architectures that support the insn. */ 3193 needed_arch_mask &= ~SPARC_OPCODE_SUPPORTED (max_architecture); 3194 p = required_archs; 3195 arch = sparc_ffs (needed_arch_mask); 3196 while ((1 << arch) <= needed_arch_mask) 3197 { 3198 if ((1 << arch) & needed_arch_mask) 3199 { 3200 if (printed_one_p) 3201 *p++ = '|'; 3202 strcpy (p, sparc_opcode_archs[arch].name); 3203 p += strlen (p); 3204 printed_one_p = 1; 3205 } 3206 ++arch; 3207 } 3208 3209 as_bad (_("Architecture mismatch on \"%s\"."), str); 3210 as_tsktsk (_(" (Requires %s; requested architecture is %s.)"), 3211 required_archs, 3212 sparc_opcode_archs[max_architecture].name); 3213 return special_case; 3214 } 3215 3216 /* Make sure the hwcaps used by the instruction are 3217 currently enabled. */ 3218 if (hwcaps & ~hwcap_allowed) 3219 { 3220 const char *hwcap_name = get_hwcap_name(hwcaps & ~hwcap_allowed); 3221 3222 as_bad (_("Hardware capability \"%s\" not enabled for \"%s\"."), 3223 hwcap_name, str); 3224 return special_case; 3225 } 3226 } /* If no match. */ 3227 3228 break; 3229 } /* Forever looking for a match. */ 3230 3231 the_insn.opcode = opcode; 3232 return special_case; 3233 } 3234 3235 /* Parse an argument that can be expressed as a keyword. 3236 (eg: #StoreStore or %ccfr). 3237 The result is a boolean indicating success. 3238 If successful, INPUT_POINTER is updated. */ 3239 3240 static int 3241 parse_keyword_arg (int (*lookup_fn) (const char *), 3242 char **input_pointerP, 3243 int *valueP) 3244 { 3245 int value; 3246 char c, *p, *q; 3247 3248 p = *input_pointerP; 3249 for (q = p + (*p == '#' || *p == '%'); 3250 ISALNUM (*q) || *q == '_'; 3251 ++q) 3252 continue; 3253 c = *q; 3254 *q = 0; 3255 value = (*lookup_fn) (p); 3256 *q = c; 3257 if (value == -1) 3258 return 0; 3259 *valueP = value; 3260 *input_pointerP = q; 3261 return 1; 3262 } 3263 3264 /* Parse an argument that is a constant expression. 3265 The result is a boolean indicating success. */ 3266 3267 static int 3268 parse_const_expr_arg (char **input_pointerP, int *valueP) 3269 { 3270 char *save = input_line_pointer; 3271 expressionS exp; 3272 3273 input_line_pointer = *input_pointerP; 3274 /* The next expression may be something other than a constant 3275 (say if we're not processing the right variant of the insn). 3276 Don't call expression unless we're sure it will succeed as it will 3277 signal an error (which we want to defer until later). */ 3278 /* FIXME: It might be better to define md_operand and have it recognize 3279 things like %asi, etc. but continuing that route through to the end 3280 is a lot of work. */ 3281 if (*input_line_pointer == '%') 3282 { 3283 input_line_pointer = save; 3284 return 0; 3285 } 3286 expression (&exp); 3287 *input_pointerP = input_line_pointer; 3288 input_line_pointer = save; 3289 if (exp.X_op != O_constant) 3290 return 0; 3291 *valueP = exp.X_add_number; 3292 return 1; 3293 } 3294 3295 /* Subroutine of sparc_ip to parse an expression. */ 3296 3297 static int 3298 get_expression (char *str) 3299 { 3300 char *save_in; 3301 segT seg; 3302 3303 save_in = input_line_pointer; 3304 input_line_pointer = str; 3305 seg = expression (&the_insn.exp); 3306 if (seg != absolute_section 3307 && seg != text_section 3308 && seg != data_section 3309 && seg != bss_section 3310 && seg != undefined_section) 3311 { 3312 the_insn.error = _("bad segment"); 3313 expr_end = input_line_pointer; 3314 input_line_pointer = save_in; 3315 return 1; 3316 } 3317 expr_end = input_line_pointer; 3318 input_line_pointer = save_in; 3319 return 0; 3320 } 3321 3322 /* Subroutine of md_assemble to output one insn. */ 3323 3324 static void 3325 output_insn (const struct sparc_opcode *insn, struct sparc_it *theinsn) 3326 { 3327 char *toP = frag_more (4); 3328 3329 /* Put out the opcode. */ 3330 if (INSN_BIG_ENDIAN) 3331 number_to_chars_bigendian (toP, (valueT) theinsn->opcode, 4); 3332 else 3333 number_to_chars_littleendian (toP, (valueT) theinsn->opcode, 4); 3334 3335 /* Put out the symbol-dependent stuff. */ 3336 if (theinsn->reloc != BFD_RELOC_NONE) 3337 { 3338 fixS *fixP = fix_new_exp (frag_now, /* Which frag. */ 3339 (toP - frag_now->fr_literal), /* Where. */ 3340 4, /* Size. */ 3341 &theinsn->exp, 3342 theinsn->pcrel, 3343 theinsn->reloc); 3344 /* Turn off overflow checking in fixup_segment. We'll do our 3345 own overflow checking in md_apply_fix. This is necessary because 3346 the insn size is 4 and fixup_segment will signal an overflow for 3347 large 8 byte quantities. */ 3348 fixP->fx_no_overflow = 1; 3349 if (theinsn->reloc == BFD_RELOC_SPARC_OLO10) 3350 fixP->tc_fix_data = theinsn->exp2.X_add_number; 3351 } 3352 3353 last_insn = insn; 3354 last_opcode = theinsn->opcode; 3355 3356 #ifdef OBJ_ELF 3357 dwarf2_emit_insn (4); 3358 #endif 3359 } 3360 3361 const char * 3363 md_atof (int type, char *litP, int *sizeP) 3364 { 3365 return ieee_md_atof (type, litP, sizeP, target_big_endian); 3366 } 3367 3368 /* Write a value out to the object file, using the appropriate 3369 endianness. */ 3370 3371 void 3372 md_number_to_chars (char *buf, valueT val, int n) 3373 { 3374 if (target_big_endian) 3375 number_to_chars_bigendian (buf, val, n); 3376 else if (target_little_endian_data 3377 && ((n == 4 || n == 2) && ~now_seg->flags & SEC_ALLOC)) 3378 /* Output debug words, which are not in allocated sections, as big 3379 endian. */ 3380 number_to_chars_bigendian (buf, val, n); 3381 else if (target_little_endian_data || ! target_big_endian) 3382 number_to_chars_littleendian (buf, val, n); 3383 } 3384 3385 /* Apply a fixS to the frags, now that we know the value it ought to 3387 hold. */ 3388 3389 void 3390 md_apply_fix (fixS *fixP, valueT *valP, segT segment ATTRIBUTE_UNUSED) 3391 { 3392 char *buf = fixP->fx_where + fixP->fx_frag->fr_literal; 3393 offsetT val = * (offsetT *) valP; 3394 long insn; 3395 3396 gas_assert (fixP->fx_r_type < BFD_RELOC_UNUSED); 3397 3398 fixP->fx_addnumber = val; /* Remember value for emit_reloc. */ 3399 3400 #ifdef OBJ_ELF 3401 /* SPARC ELF relocations don't use an addend in the data field. */ 3402 if (fixP->fx_addsy != NULL) 3403 { 3404 switch (fixP->fx_r_type) 3405 { 3406 case BFD_RELOC_SPARC_TLS_GD_HI22: 3407 case BFD_RELOC_SPARC_TLS_GD_LO10: 3408 case BFD_RELOC_SPARC_TLS_GD_ADD: 3409 case BFD_RELOC_SPARC_TLS_GD_CALL: 3410 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3411 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3412 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3413 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3414 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3415 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3416 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3417 case BFD_RELOC_SPARC_TLS_IE_HI22: 3418 case BFD_RELOC_SPARC_TLS_IE_LO10: 3419 case BFD_RELOC_SPARC_TLS_IE_LD: 3420 case BFD_RELOC_SPARC_TLS_IE_LDX: 3421 case BFD_RELOC_SPARC_TLS_IE_ADD: 3422 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3423 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3424 case BFD_RELOC_SPARC_TLS_DTPMOD32: 3425 case BFD_RELOC_SPARC_TLS_DTPMOD64: 3426 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3427 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3428 case BFD_RELOC_SPARC_TLS_TPOFF32: 3429 case BFD_RELOC_SPARC_TLS_TPOFF64: 3430 S_SET_THREAD_LOCAL (fixP->fx_addsy); 3431 3432 default: 3433 break; 3434 } 3435 3436 return; 3437 } 3438 #endif 3439 3440 /* This is a hack. There should be a better way to 3441 handle this. Probably in terms of howto fields, once 3442 we can look at these fixups in terms of howtos. */ 3443 if (fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 && fixP->fx_addsy) 3444 val += fixP->fx_where + fixP->fx_frag->fr_address; 3445 3446 #ifdef OBJ_AOUT 3447 /* FIXME: More ridiculous gas reloc hacking. If we are going to 3448 generate a reloc, then we just want to let the reloc addend set 3449 the value. We do not want to also stuff the addend into the 3450 object file. Including the addend in the object file works when 3451 doing a static link, because the linker will ignore the object 3452 file contents. However, the dynamic linker does not ignore the 3453 object file contents. */ 3454 if (fixP->fx_addsy != NULL 3455 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2) 3456 val = 0; 3457 3458 /* When generating PIC code, we do not want an addend for a reloc 3459 against a local symbol. We adjust fx_addnumber to cancel out the 3460 value already included in val, and to also cancel out the 3461 adjustment which bfd_install_relocation will create. */ 3462 if (sparc_pic_code 3463 && fixP->fx_r_type != BFD_RELOC_32_PCREL_S2 3464 && fixP->fx_addsy != NULL 3465 && ! S_IS_COMMON (fixP->fx_addsy) 3466 && symbol_section_p (fixP->fx_addsy)) 3467 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3468 3469 /* When generating PIC code, we need to fiddle to get 3470 bfd_install_relocation to do the right thing for a PC relative 3471 reloc against a local symbol which we are going to keep. */ 3472 if (sparc_pic_code 3473 && fixP->fx_r_type == BFD_RELOC_32_PCREL_S2 3474 && fixP->fx_addsy != NULL 3475 && (S_IS_EXTERNAL (fixP->fx_addsy) 3476 || S_IS_WEAK (fixP->fx_addsy)) 3477 && S_IS_DEFINED (fixP->fx_addsy) 3478 && ! S_IS_COMMON (fixP->fx_addsy)) 3479 { 3480 val = 0; 3481 fixP->fx_addnumber -= 2 * S_GET_VALUE (fixP->fx_addsy); 3482 } 3483 #endif 3484 3485 /* If this is a data relocation, just output VAL. */ 3486 3487 if (fixP->fx_r_type == BFD_RELOC_8) 3488 { 3489 md_number_to_chars (buf, val, 1); 3490 } 3491 else if (fixP->fx_r_type == BFD_RELOC_16 3492 || fixP->fx_r_type == BFD_RELOC_SPARC_UA16) 3493 { 3494 md_number_to_chars (buf, val, 2); 3495 } 3496 else if (fixP->fx_r_type == BFD_RELOC_32 3497 || fixP->fx_r_type == BFD_RELOC_SPARC_UA32 3498 || fixP->fx_r_type == BFD_RELOC_SPARC_REV32) 3499 { 3500 md_number_to_chars (buf, val, 4); 3501 } 3502 else if (fixP->fx_r_type == BFD_RELOC_64 3503 || fixP->fx_r_type == BFD_RELOC_SPARC_UA64) 3504 { 3505 md_number_to_chars (buf, val, 8); 3506 } 3507 else if (fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT 3508 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) 3509 { 3510 fixP->fx_done = 0; 3511 return; 3512 } 3513 else 3514 { 3515 /* It's a relocation against an instruction. */ 3516 3517 if (INSN_BIG_ENDIAN) 3518 insn = bfd_getb32 ((unsigned char *) buf); 3519 else 3520 insn = bfd_getl32 ((unsigned char *) buf); 3521 3522 switch (fixP->fx_r_type) 3523 { 3524 case BFD_RELOC_32_PCREL_S2: 3525 val = val >> 2; 3526 /* FIXME: This increment-by-one deserves a comment of why it's 3527 being done! */ 3528 if (! sparc_pic_code 3529 || fixP->fx_addsy == NULL 3530 || symbol_section_p (fixP->fx_addsy)) 3531 ++val; 3532 3533 insn |= val & 0x3fffffff; 3534 3535 /* See if we have a delay slot. */ 3536 if (sparc_relax && fixP->fx_where + 8 <= fixP->fx_frag->fr_fix) 3537 { 3538 #define G0 0 3539 #define O7 15 3540 #define XCC (2 << 20) 3541 #define COND(x) (((x)&0xf)<<25) 3542 #define CONDA COND(0x8) 3543 #define INSN_BPA (F2(0,1) | CONDA | BPRED | XCC) 3544 #define INSN_BA (F2(0,2) | CONDA) 3545 #define INSN_OR F3(2, 0x2, 0) 3546 #define INSN_NOP F2(0,4) 3547 3548 long delay; 3549 3550 /* If the instruction is a call with either: 3551 restore 3552 arithmetic instruction with rd == %o7 3553 where rs1 != %o7 and rs2 if it is register != %o7 3554 then we can optimize if the call destination is near 3555 by changing the call into a branch always. */ 3556 if (INSN_BIG_ENDIAN) 3557 delay = bfd_getb32 ((unsigned char *) buf + 4); 3558 else 3559 delay = bfd_getl32 ((unsigned char *) buf + 4); 3560 if ((insn & OP (~0)) != OP (1) || (delay & OP (~0)) != OP (2)) 3561 break; 3562 if ((delay & OP3 (~0)) != OP3 (0x3d) /* Restore. */ 3563 && ((delay & OP3 (0x28)) != 0 /* Arithmetic. */ 3564 || ((delay & RD (~0)) != RD (O7)))) 3565 break; 3566 if ((delay & RS1 (~0)) == RS1 (O7) 3567 || ((delay & F3I (~0)) == 0 3568 && (delay & RS2 (~0)) == RS2 (O7))) 3569 break; 3570 /* Ensure the branch will fit into simm22. */ 3571 if ((val & 0x3fe00000) 3572 && (val & 0x3fe00000) != 0x3fe00000) 3573 break; 3574 /* Check if the arch is v9 and branch will fit 3575 into simm19. */ 3576 if (((val & 0x3c0000) == 0 3577 || (val & 0x3c0000) == 0x3c0000) 3578 && (sparc_arch_size == 64 3579 || current_architecture >= SPARC_OPCODE_ARCH_V9)) 3580 /* ba,pt %xcc */ 3581 insn = INSN_BPA | (val & 0x7ffff); 3582 else 3583 /* ba */ 3584 insn = INSN_BA | (val & 0x3fffff); 3585 if (fixP->fx_where >= 4 3586 && ((delay & (0xffffffff ^ RS1 (~0))) 3587 == (INSN_OR | RD (O7) | RS2 (G0)))) 3588 { 3589 long setter; 3590 int reg; 3591 3592 if (INSN_BIG_ENDIAN) 3593 setter = bfd_getb32 ((unsigned char *) buf - 4); 3594 else 3595 setter = bfd_getl32 ((unsigned char *) buf - 4); 3596 if ((setter & (0xffffffff ^ RD (~0))) 3597 != (INSN_OR | RS1 (O7) | RS2 (G0))) 3598 break; 3599 /* The sequence was 3600 or %o7, %g0, %rN 3601 call foo 3602 or %rN, %g0, %o7 3603 3604 If call foo was replaced with ba, replace 3605 or %rN, %g0, %o7 with nop. */ 3606 reg = (delay & RS1 (~0)) >> 14; 3607 if (reg != ((setter & RD (~0)) >> 25) 3608 || reg == G0 || reg == O7) 3609 break; 3610 3611 if (INSN_BIG_ENDIAN) 3612 bfd_putb32 (INSN_NOP, (unsigned char *) buf + 4); 3613 else 3614 bfd_putl32 (INSN_NOP, (unsigned char *) buf + 4); 3615 } 3616 } 3617 break; 3618 3619 case BFD_RELOC_SPARC_11: 3620 if (! in_signed_range (val, 0x7ff)) 3621 as_bad_where (fixP->fx_file, fixP->fx_line, 3622 _("relocation overflow")); 3623 insn |= val & 0x7ff; 3624 break; 3625 3626 case BFD_RELOC_SPARC_10: 3627 if (! in_signed_range (val, 0x3ff)) 3628 as_bad_where (fixP->fx_file, fixP->fx_line, 3629 _("relocation overflow")); 3630 insn |= val & 0x3ff; 3631 break; 3632 3633 case BFD_RELOC_SPARC_7: 3634 if (! in_bitfield_range (val, 0x7f)) 3635 as_bad_where (fixP->fx_file, fixP->fx_line, 3636 _("relocation overflow")); 3637 insn |= val & 0x7f; 3638 break; 3639 3640 case BFD_RELOC_SPARC_6: 3641 if (! in_bitfield_range (val, 0x3f)) 3642 as_bad_where (fixP->fx_file, fixP->fx_line, 3643 _("relocation overflow")); 3644 insn |= val & 0x3f; 3645 break; 3646 3647 case BFD_RELOC_SPARC_5: 3648 if (! in_bitfield_range (val, 0x1f)) 3649 as_bad_where (fixP->fx_file, fixP->fx_line, 3650 _("relocation overflow")); 3651 insn |= val & 0x1f; 3652 break; 3653 3654 case BFD_RELOC_SPARC_WDISP10: 3655 if ((val & 3) 3656 || val >= 0x007fc 3657 || val <= -(offsetT) 0x808) 3658 as_bad_where (fixP->fx_file, fixP->fx_line, 3659 _("relocation overflow")); 3660 /* FIXME: The +1 deserves a comment. */ 3661 val = (val >> 2) + 1; 3662 insn |= ((val & 0x300) << 11) 3663 | ((val & 0xff) << 5); 3664 break; 3665 3666 case BFD_RELOC_SPARC_WDISP16: 3667 if ((val & 3) 3668 || val >= 0x1fffc 3669 || val <= -(offsetT) 0x20008) 3670 as_bad_where (fixP->fx_file, fixP->fx_line, 3671 _("relocation overflow")); 3672 /* FIXME: The +1 deserves a comment. */ 3673 val = (val >> 2) + 1; 3674 insn |= ((val & 0xc000) << 6) | (val & 0x3fff); 3675 break; 3676 3677 case BFD_RELOC_SPARC_WDISP19: 3678 if ((val & 3) 3679 || val >= 0xffffc 3680 || val <= -(offsetT) 0x100008) 3681 as_bad_where (fixP->fx_file, fixP->fx_line, 3682 _("relocation overflow")); 3683 /* FIXME: The +1 deserves a comment. */ 3684 val = (val >> 2) + 1; 3685 insn |= val & 0x7ffff; 3686 break; 3687 3688 case BFD_RELOC_SPARC_HH22: 3689 val = BSR (val, 32); 3690 /* Fall through. */ 3691 3692 case BFD_RELOC_SPARC_LM22: 3693 case BFD_RELOC_HI22: 3694 if (!fixP->fx_addsy) 3695 insn |= (val >> 10) & 0x3fffff; 3696 else 3697 /* FIXME: Need comment explaining why we do this. */ 3698 insn &= ~0xffff; 3699 break; 3700 3701 case BFD_RELOC_SPARC22: 3702 if (val & ~0x003fffff) 3703 as_bad_where (fixP->fx_file, fixP->fx_line, 3704 _("relocation overflow")); 3705 insn |= (val & 0x3fffff); 3706 break; 3707 3708 case BFD_RELOC_SPARC_HM10: 3709 val = BSR (val, 32); 3710 /* Fall through. */ 3711 3712 case BFD_RELOC_LO10: 3713 if (!fixP->fx_addsy) 3714 insn |= val & 0x3ff; 3715 else 3716 /* FIXME: Need comment explaining why we do this. */ 3717 insn &= ~0xff; 3718 break; 3719 3720 case BFD_RELOC_SPARC_OLO10: 3721 val &= 0x3ff; 3722 val += fixP->tc_fix_data; 3723 /* Fall through. */ 3724 3725 case BFD_RELOC_SPARC13: 3726 if (! in_signed_range (val, 0x1fff)) 3727 as_bad_where (fixP->fx_file, fixP->fx_line, 3728 _("relocation overflow")); 3729 insn |= val & 0x1fff; 3730 break; 3731 3732 case BFD_RELOC_SPARC_WDISP22: 3733 val = (val >> 2) + 1; 3734 /* Fall through. */ 3735 case BFD_RELOC_SPARC_BASE22: 3736 insn |= val & 0x3fffff; 3737 break; 3738 3739 case BFD_RELOC_SPARC_H34: 3740 if (!fixP->fx_addsy) 3741 { 3742 bfd_vma tval = val; 3743 tval >>= 12; 3744 insn |= tval & 0x3fffff; 3745 } 3746 break; 3747 3748 case BFD_RELOC_SPARC_H44: 3749 if (!fixP->fx_addsy) 3750 { 3751 bfd_vma tval = val; 3752 tval >>= 22; 3753 insn |= tval & 0x3fffff; 3754 } 3755 break; 3756 3757 case BFD_RELOC_SPARC_M44: 3758 if (!fixP->fx_addsy) 3759 insn |= (val >> 12) & 0x3ff; 3760 break; 3761 3762 case BFD_RELOC_SPARC_L44: 3763 if (!fixP->fx_addsy) 3764 insn |= val & 0xfff; 3765 break; 3766 3767 case BFD_RELOC_SPARC_HIX22: 3768 if (!fixP->fx_addsy) 3769 { 3770 val ^= ~(offsetT) 0; 3771 insn |= (val >> 10) & 0x3fffff; 3772 } 3773 break; 3774 3775 case BFD_RELOC_SPARC_LOX10: 3776 if (!fixP->fx_addsy) 3777 insn |= 0x1c00 | (val & 0x3ff); 3778 break; 3779 3780 case BFD_RELOC_NONE: 3781 default: 3782 as_bad_where (fixP->fx_file, fixP->fx_line, 3783 _("bad or unhandled relocation type: 0x%02x"), 3784 fixP->fx_r_type); 3785 break; 3786 } 3787 3788 if (INSN_BIG_ENDIAN) 3789 bfd_putb32 (insn, (unsigned char *) buf); 3790 else 3791 bfd_putl32 (insn, (unsigned char *) buf); 3792 } 3793 3794 /* Are we finished with this relocation now? */ 3795 if (fixP->fx_addsy == 0 && !fixP->fx_pcrel) 3796 fixP->fx_done = 1; 3797 } 3798 3799 /* Translate internal representation of relocation info to BFD target 3800 format. */ 3801 3802 arelent ** 3803 tc_gen_reloc (asection *section, fixS *fixp) 3804 { 3805 static arelent *relocs[3]; 3806 arelent *reloc; 3807 bfd_reloc_code_real_type code; 3808 3809 relocs[0] = reloc = XNEW (arelent); 3810 relocs[1] = NULL; 3811 3812 reloc->sym_ptr_ptr = XNEW (asymbol *); 3813 *reloc->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); 3814 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 3815 3816 switch (fixp->fx_r_type) 3817 { 3818 case BFD_RELOC_16: 3819 case BFD_RELOC_32: 3820 case BFD_RELOC_HI22: 3821 case BFD_RELOC_LO10: 3822 case BFD_RELOC_32_PCREL_S2: 3823 case BFD_RELOC_SPARC13: 3824 case BFD_RELOC_SPARC22: 3825 case BFD_RELOC_SPARC_PC22: 3826 case BFD_RELOC_SPARC_PC10: 3827 case BFD_RELOC_SPARC_BASE13: 3828 case BFD_RELOC_SPARC_WDISP10: 3829 case BFD_RELOC_SPARC_WDISP16: 3830 case BFD_RELOC_SPARC_WDISP19: 3831 case BFD_RELOC_SPARC_WDISP22: 3832 case BFD_RELOC_64: 3833 case BFD_RELOC_SPARC_5: 3834 case BFD_RELOC_SPARC_6: 3835 case BFD_RELOC_SPARC_7: 3836 case BFD_RELOC_SPARC_10: 3837 case BFD_RELOC_SPARC_11: 3838 case BFD_RELOC_SPARC_HH22: 3839 case BFD_RELOC_SPARC_HM10: 3840 case BFD_RELOC_SPARC_LM22: 3841 case BFD_RELOC_SPARC_PC_HH22: 3842 case BFD_RELOC_SPARC_PC_HM10: 3843 case BFD_RELOC_SPARC_PC_LM22: 3844 case BFD_RELOC_SPARC_H34: 3845 case BFD_RELOC_SPARC_H44: 3846 case BFD_RELOC_SPARC_M44: 3847 case BFD_RELOC_SPARC_L44: 3848 case BFD_RELOC_SPARC_HIX22: 3849 case BFD_RELOC_SPARC_LOX10: 3850 case BFD_RELOC_SPARC_REV32: 3851 case BFD_RELOC_SPARC_OLO10: 3852 case BFD_RELOC_SPARC_UA16: 3853 case BFD_RELOC_SPARC_UA32: 3854 case BFD_RELOC_SPARC_UA64: 3855 case BFD_RELOC_8_PCREL: 3856 case BFD_RELOC_16_PCREL: 3857 case BFD_RELOC_32_PCREL: 3858 case BFD_RELOC_64_PCREL: 3859 case BFD_RELOC_SPARC_PLT32: 3860 case BFD_RELOC_SPARC_PLT64: 3861 case BFD_RELOC_VTABLE_ENTRY: 3862 case BFD_RELOC_VTABLE_INHERIT: 3863 case BFD_RELOC_SPARC_TLS_GD_HI22: 3864 case BFD_RELOC_SPARC_TLS_GD_LO10: 3865 case BFD_RELOC_SPARC_TLS_GD_ADD: 3866 case BFD_RELOC_SPARC_TLS_GD_CALL: 3867 case BFD_RELOC_SPARC_TLS_LDM_HI22: 3868 case BFD_RELOC_SPARC_TLS_LDM_LO10: 3869 case BFD_RELOC_SPARC_TLS_LDM_ADD: 3870 case BFD_RELOC_SPARC_TLS_LDM_CALL: 3871 case BFD_RELOC_SPARC_TLS_LDO_HIX22: 3872 case BFD_RELOC_SPARC_TLS_LDO_LOX10: 3873 case BFD_RELOC_SPARC_TLS_LDO_ADD: 3874 case BFD_RELOC_SPARC_TLS_IE_HI22: 3875 case BFD_RELOC_SPARC_TLS_IE_LO10: 3876 case BFD_RELOC_SPARC_TLS_IE_LD: 3877 case BFD_RELOC_SPARC_TLS_IE_LDX: 3878 case BFD_RELOC_SPARC_TLS_IE_ADD: 3879 case BFD_RELOC_SPARC_TLS_LE_HIX22: 3880 case BFD_RELOC_SPARC_TLS_LE_LOX10: 3881 case BFD_RELOC_SPARC_TLS_DTPOFF32: 3882 case BFD_RELOC_SPARC_TLS_DTPOFF64: 3883 case BFD_RELOC_SPARC_GOTDATA_OP_HIX22: 3884 case BFD_RELOC_SPARC_GOTDATA_OP_LOX10: 3885 case BFD_RELOC_SPARC_GOTDATA_OP: 3886 code = fixp->fx_r_type; 3887 break; 3888 default: 3889 abort (); 3890 return NULL; 3891 } 3892 3893 #if defined (OBJ_ELF) || defined (OBJ_AOUT) 3894 /* If we are generating PIC code, we need to generate a different 3895 set of relocs. */ 3896 3897 #ifdef OBJ_ELF 3898 #define GOT_NAME "_GLOBAL_OFFSET_TABLE_" 3899 #else 3900 #define GOT_NAME "__GLOBAL_OFFSET_TABLE_" 3901 #endif 3902 #ifdef TE_VXWORKS 3903 #define GOTT_BASE "__GOTT_BASE__" 3904 #define GOTT_INDEX "__GOTT_INDEX__" 3905 #endif 3906 3907 /* This code must be parallel to the OBJ_ELF tc_fix_adjustable. */ 3908 3909 if (sparc_pic_code) 3910 { 3911 switch (code) 3912 { 3913 case BFD_RELOC_32_PCREL_S2: 3914 if (generic_force_reloc (fixp)) 3915 code = BFD_RELOC_SPARC_WPLT30; 3916 break; 3917 case BFD_RELOC_HI22: 3918 code = BFD_RELOC_SPARC_GOT22; 3919 if (fixp->fx_addsy != NULL) 3920 { 3921 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3922 code = BFD_RELOC_SPARC_PC22; 3923 #ifdef TE_VXWORKS 3924 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3925 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3926 code = BFD_RELOC_HI22; /* Unchanged. */ 3927 #endif 3928 } 3929 break; 3930 case BFD_RELOC_LO10: 3931 code = BFD_RELOC_SPARC_GOT10; 3932 if (fixp->fx_addsy != NULL) 3933 { 3934 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOT_NAME) == 0) 3935 code = BFD_RELOC_SPARC_PC10; 3936 #ifdef TE_VXWORKS 3937 if (strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_BASE) == 0 3938 || strcmp (S_GET_NAME (fixp->fx_addsy), GOTT_INDEX) == 0) 3939 code = BFD_RELOC_LO10; /* Unchanged. */ 3940 #endif 3941 } 3942 break; 3943 case BFD_RELOC_SPARC13: 3944 code = BFD_RELOC_SPARC_GOT13; 3945 break; 3946 default: 3947 break; 3948 } 3949 } 3950 #endif /* defined (OBJ_ELF) || defined (OBJ_AOUT) */ 3951 3952 /* Nothing is aligned in DWARF debugging sections. */ 3953 if (bfd_get_section_flags (stdoutput, section) & SEC_DEBUGGING) 3954 switch (code) 3955 { 3956 case BFD_RELOC_16: code = BFD_RELOC_SPARC_UA16; break; 3957 case BFD_RELOC_32: code = BFD_RELOC_SPARC_UA32; break; 3958 case BFD_RELOC_64: code = BFD_RELOC_SPARC_UA64; break; 3959 default: break; 3960 } 3961 3962 if (code == BFD_RELOC_SPARC_OLO10) 3963 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_LO10); 3964 else 3965 reloc->howto = bfd_reloc_type_lookup (stdoutput, code); 3966 if (reloc->howto == 0) 3967 { 3968 as_bad_where (fixp->fx_file, fixp->fx_line, 3969 _("internal error: can't export reloc type %d (`%s')"), 3970 fixp->fx_r_type, bfd_get_reloc_code_name (code)); 3971 xfree (reloc); 3972 relocs[0] = NULL; 3973 return relocs; 3974 } 3975 3976 /* @@ Why fx_addnumber sometimes and fx_offset other times? */ 3977 #ifdef OBJ_AOUT 3978 3979 if (reloc->howto->pc_relative == 0 3980 || code == BFD_RELOC_SPARC_PC10 3981 || code == BFD_RELOC_SPARC_PC22) 3982 reloc->addend = fixp->fx_addnumber; 3983 else if (sparc_pic_code 3984 && fixp->fx_r_type == BFD_RELOC_32_PCREL_S2 3985 && fixp->fx_addsy != NULL 3986 && (S_IS_EXTERNAL (fixp->fx_addsy) 3987 || S_IS_WEAK (fixp->fx_addsy)) 3988 && S_IS_DEFINED (fixp->fx_addsy) 3989 && ! S_IS_COMMON (fixp->fx_addsy)) 3990 reloc->addend = fixp->fx_addnumber; 3991 else 3992 reloc->addend = fixp->fx_offset - reloc->address; 3993 3994 #else /* elf or coff */ 3995 3996 if (code != BFD_RELOC_32_PCREL_S2 3997 && code != BFD_RELOC_SPARC_WDISP22 3998 && code != BFD_RELOC_SPARC_WDISP16 3999 && code != BFD_RELOC_SPARC_WDISP19 4000 && code != BFD_RELOC_SPARC_WDISP10 4001 && code != BFD_RELOC_SPARC_WPLT30 4002 && code != BFD_RELOC_SPARC_TLS_GD_CALL 4003 && code != BFD_RELOC_SPARC_TLS_LDM_CALL) 4004 reloc->addend = fixp->fx_addnumber; 4005 else if (symbol_section_p (fixp->fx_addsy)) 4006 reloc->addend = (section->vma 4007 + fixp->fx_addnumber 4008 + md_pcrel_from (fixp)); 4009 else 4010 reloc->addend = fixp->fx_offset; 4011 #endif 4012 4013 /* We expand R_SPARC_OLO10 to R_SPARC_LO10 and R_SPARC_13 4014 on the same location. */ 4015 if (code == BFD_RELOC_SPARC_OLO10) 4016 { 4017 relocs[1] = reloc = XNEW (arelent); 4018 relocs[2] = NULL; 4019 4020 reloc->sym_ptr_ptr = XNEW (asymbol *); 4021 *reloc->sym_ptr_ptr 4022 = symbol_get_bfdsym (section_symbol (absolute_section)); 4023 reloc->address = fixp->fx_frag->fr_address + fixp->fx_where; 4024 reloc->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_SPARC13); 4025 reloc->addend = fixp->tc_fix_data; 4026 } 4027 4028 return relocs; 4029 } 4030 4031 /* We have no need to default values of symbols. */ 4033 4034 symbolS * 4035 md_undefined_symbol (char *name ATTRIBUTE_UNUSED) 4036 { 4037 return 0; 4038 } 4039 4040 /* Round up a section size to the appropriate boundary. */ 4041 4042 valueT 4043 md_section_align (segT segment ATTRIBUTE_UNUSED, valueT size) 4044 { 4045 #ifndef OBJ_ELF 4046 /* This is not right for ELF; a.out wants it, and COFF will force 4047 the alignment anyways. */ 4048 valueT align = ((valueT) 1 4049 << (valueT) bfd_get_section_alignment (stdoutput, segment)); 4050 valueT newsize; 4051 4052 /* Turn alignment value into a mask. */ 4053 align--; 4054 newsize = (size + align) & ~align; 4055 return newsize; 4056 #else 4057 return size; 4058 #endif 4059 } 4060 4061 /* Exactly what point is a PC-relative offset relative TO? 4062 On the sparc, they're relative to the address of the offset, plus 4063 its size. This gets us to the following instruction. 4064 (??? Is this right? FIXME-SOON) */ 4065 long 4066 md_pcrel_from (fixS *fixP) 4067 { 4068 long ret; 4069 4070 ret = fixP->fx_where + fixP->fx_frag->fr_address; 4071 if (! sparc_pic_code 4072 || fixP->fx_addsy == NULL 4073 || symbol_section_p (fixP->fx_addsy)) 4074 ret += fixP->fx_size; 4075 return ret; 4076 } 4077 4078 /* Return log2 (VALUE), or -1 if VALUE is not an exact positive power 4080 of two. */ 4081 4082 static int 4083 mylog2 (int value) 4084 { 4085 int shift; 4086 4087 if (value <= 0) 4088 return -1; 4089 4090 for (shift = 0; (value & 1) == 0; value >>= 1) 4091 ++shift; 4092 4093 return (value == 1) ? shift : -1; 4094 } 4095 4096 /* Sort of like s_lcomm. */ 4097 4098 #ifndef OBJ_ELF 4099 static int max_alignment = 15; 4100 #endif 4101 4102 static void 4103 s_reserve (int ignore ATTRIBUTE_UNUSED) 4104 { 4105 char *name; 4106 char *p; 4107 char c; 4108 int align; 4109 int size; 4110 int temp; 4111 symbolS *symbolP; 4112 4113 c = get_symbol_name (&name); 4114 p = input_line_pointer; 4115 *p = c; 4116 SKIP_WHITESPACE_AFTER_NAME (); 4117 4118 if (*input_line_pointer != ',') 4119 { 4120 as_bad (_("Expected comma after name")); 4121 ignore_rest_of_line (); 4122 return; 4123 } 4124 4125 ++input_line_pointer; 4126 4127 if ((size = get_absolute_expression ()) < 0) 4128 { 4129 as_bad (_("BSS length (%d.) <0! Ignored."), size); 4130 ignore_rest_of_line (); 4131 return; 4132 } /* Bad length. */ 4133 4134 *p = 0; 4135 symbolP = symbol_find_or_make (name); 4136 *p = c; 4137 4138 if (strncmp (input_line_pointer, ",\"bss\"", 6) != 0 4139 && strncmp (input_line_pointer, ",\".bss\"", 7) != 0) 4140 { 4141 as_bad (_("bad .reserve segment -- expected BSS segment")); 4142 return; 4143 } 4144 4145 if (input_line_pointer[2] == '.') 4146 input_line_pointer += 7; 4147 else 4148 input_line_pointer += 6; 4149 SKIP_WHITESPACE (); 4150 4151 if (*input_line_pointer == ',') 4152 { 4153 ++input_line_pointer; 4154 4155 SKIP_WHITESPACE (); 4156 if (*input_line_pointer == '\n') 4157 { 4158 as_bad (_("missing alignment")); 4159 ignore_rest_of_line (); 4160 return; 4161 } 4162 4163 align = (int) get_absolute_expression (); 4164 4165 #ifndef OBJ_ELF 4166 if (align > max_alignment) 4167 { 4168 align = max_alignment; 4169 as_warn (_("alignment too large; assuming %d"), align); 4170 } 4171 #endif 4172 4173 if (align < 0) 4174 { 4175 as_bad (_("negative alignment")); 4176 ignore_rest_of_line (); 4177 return; 4178 } 4179 4180 if (align != 0) 4181 { 4182 temp = mylog2 (align); 4183 if (temp < 0) 4184 { 4185 as_bad (_("alignment not a power of 2")); 4186 ignore_rest_of_line (); 4187 return; 4188 } 4189 4190 align = temp; 4191 } 4192 4193 record_alignment (bss_section, align); 4194 } 4195 else 4196 align = 0; 4197 4198 if (!S_IS_DEFINED (symbolP) 4199 #ifdef OBJ_AOUT 4200 && S_GET_OTHER (symbolP) == 0 4201 && S_GET_DESC (symbolP) == 0 4202 #endif 4203 ) 4204 { 4205 if (! need_pass_2) 4206 { 4207 char *pfrag; 4208 segT current_seg = now_seg; 4209 subsegT current_subseg = now_subseg; 4210 4211 /* Switch to bss. */ 4212 subseg_set (bss_section, 1); 4213 4214 if (align) 4215 /* Do alignment. */ 4216 frag_align (align, 0, 0); 4217 4218 /* Detach from old frag. */ 4219 if (S_GET_SEGMENT (symbolP) == bss_section) 4220 symbol_get_frag (symbolP)->fr_symbol = NULL; 4221 4222 symbol_set_frag (symbolP, frag_now); 4223 pfrag = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4224 (offsetT) size, (char *) 0); 4225 *pfrag = 0; 4226 4227 S_SET_SEGMENT (symbolP, bss_section); 4228 4229 subseg_set (current_seg, current_subseg); 4230 4231 #ifdef OBJ_ELF 4232 S_SET_SIZE (symbolP, size); 4233 #endif 4234 } 4235 } 4236 else 4237 { 4238 as_warn (_("Ignoring attempt to re-define symbol %s"), 4239 S_GET_NAME (symbolP)); 4240 } 4241 4242 demand_empty_rest_of_line (); 4243 } 4244 4245 static void 4246 s_common (int ignore ATTRIBUTE_UNUSED) 4247 { 4248 char *name; 4249 char c; 4250 char *p; 4251 offsetT temp, size; 4252 symbolS *symbolP; 4253 4254 c = get_symbol_name (&name); 4255 /* Just after name is now '\0'. */ 4256 p = input_line_pointer; 4257 *p = c; 4258 SKIP_WHITESPACE_AFTER_NAME (); 4259 if (*input_line_pointer != ',') 4260 { 4261 as_bad (_("Expected comma after symbol-name")); 4262 ignore_rest_of_line (); 4263 return; 4264 } 4265 4266 /* Skip ','. */ 4267 input_line_pointer++; 4268 4269 if ((temp = get_absolute_expression ()) < 0) 4270 { 4271 as_bad (_(".COMMon length (%lu) out of range ignored"), 4272 (unsigned long) temp); 4273 ignore_rest_of_line (); 4274 return; 4275 } 4276 size = temp; 4277 *p = 0; 4278 symbolP = symbol_find_or_make (name); 4279 *p = c; 4280 if (S_IS_DEFINED (symbolP) && ! S_IS_COMMON (symbolP)) 4281 { 4282 as_bad (_("Ignoring attempt to re-define symbol")); 4283 ignore_rest_of_line (); 4284 return; 4285 } 4286 if (S_GET_VALUE (symbolP) != 0) 4287 { 4288 if (S_GET_VALUE (symbolP) != (valueT) size) 4289 { 4290 as_warn (_("Length of .comm \"%s\" is already %ld. Not changed to %ld."), 4291 S_GET_NAME (symbolP), (long) S_GET_VALUE (symbolP), (long) size); 4292 } 4293 } 4294 else 4295 { 4296 #ifndef OBJ_ELF 4297 S_SET_VALUE (symbolP, (valueT) size); 4298 S_SET_EXTERNAL (symbolP); 4299 #endif 4300 } 4301 know (symbol_get_frag (symbolP) == &zero_address_frag); 4302 if (*input_line_pointer != ',') 4303 { 4304 as_bad (_("Expected comma after common length")); 4305 ignore_rest_of_line (); 4306 return; 4307 } 4308 input_line_pointer++; 4309 SKIP_WHITESPACE (); 4310 if (*input_line_pointer != '"') 4311 { 4312 temp = get_absolute_expression (); 4313 4314 #ifndef OBJ_ELF 4315 if (temp > max_alignment) 4316 { 4317 temp = max_alignment; 4318 as_warn (_("alignment too large; assuming %ld"), (long) temp); 4319 } 4320 #endif 4321 4322 if (temp < 0) 4323 { 4324 as_bad (_("negative alignment")); 4325 ignore_rest_of_line (); 4326 return; 4327 } 4328 4329 #ifdef OBJ_ELF 4330 if (symbol_get_obj (symbolP)->local) 4331 { 4332 segT old_sec; 4333 int old_subsec; 4334 int align; 4335 4336 old_sec = now_seg; 4337 old_subsec = now_subseg; 4338 4339 if (temp == 0) 4340 align = 0; 4341 else 4342 align = mylog2 (temp); 4343 4344 if (align < 0) 4345 { 4346 as_bad (_("alignment not a power of 2")); 4347 ignore_rest_of_line (); 4348 return; 4349 } 4350 4351 record_alignment (bss_section, align); 4352 subseg_set (bss_section, 0); 4353 if (align) 4354 frag_align (align, 0, 0); 4355 if (S_GET_SEGMENT (symbolP) == bss_section) 4356 symbol_get_frag (symbolP)->fr_symbol = 0; 4357 symbol_set_frag (symbolP, frag_now); 4358 p = frag_var (rs_org, 1, 1, (relax_substateT) 0, symbolP, 4359 (offsetT) size, (char *) 0); 4360 *p = 0; 4361 S_SET_SEGMENT (symbolP, bss_section); 4362 S_CLEAR_EXTERNAL (symbolP); 4363 S_SET_SIZE (symbolP, size); 4364 subseg_set (old_sec, old_subsec); 4365 } 4366 else 4367 #endif /* OBJ_ELF */ 4368 { 4369 allocate_common: 4370 S_SET_VALUE (symbolP, (valueT) size); 4371 #ifdef OBJ_ELF 4372 S_SET_ALIGN (symbolP, temp); 4373 S_SET_SIZE (symbolP, size); 4374 #endif 4375 S_SET_EXTERNAL (symbolP); 4376 S_SET_SEGMENT (symbolP, bfd_com_section_ptr); 4377 } 4378 } 4379 else 4380 { 4381 input_line_pointer++; 4382 /* @@ Some use the dot, some don't. Can we get some consistency?? */ 4383 if (*input_line_pointer == '.') 4384 input_line_pointer++; 4385 /* @@ Some say data, some say bss. */ 4386 if (strncmp (input_line_pointer, "bss\"", 4) 4387 && strncmp (input_line_pointer, "data\"", 5)) 4388 { 4389 while (*--input_line_pointer != '"') 4390 ; 4391 input_line_pointer--; 4392 goto bad_common_segment; 4393 } 4394 while (*input_line_pointer++ != '"') 4395 ; 4396 goto allocate_common; 4397 } 4398 4399 symbol_get_bfdsym (symbolP)->flags |= BSF_OBJECT; 4400 4401 demand_empty_rest_of_line (); 4402 return; 4403 4404 { 4405 bad_common_segment: 4406 p = input_line_pointer; 4407 while (*p && *p != '\n') 4408 p++; 4409 c = *p; 4410 *p = '\0'; 4411 as_bad (_("bad .common segment %s"), input_line_pointer + 1); 4412 *p = c; 4413 input_line_pointer = p; 4414 ignore_rest_of_line (); 4415 return; 4416 } 4417 } 4418 4419 /* Handle the .empty pseudo-op. This suppresses the warnings about 4420 invalid delay slot usage. */ 4421 4422 static void 4423 s_empty (int ignore ATTRIBUTE_UNUSED) 4424 { 4425 /* The easy way to implement is to just forget about the last 4426 instruction. */ 4427 last_insn = NULL; 4428 } 4429 4430 static void 4431 s_seg (int ignore ATTRIBUTE_UNUSED) 4432 { 4433 4434 if (strncmp (input_line_pointer, "\"text\"", 6) == 0) 4435 { 4436 input_line_pointer += 6; 4437 s_text (0); 4438 return; 4439 } 4440 if (strncmp (input_line_pointer, "\"data\"", 6) == 0) 4441 { 4442 input_line_pointer += 6; 4443 s_data (0); 4444 return; 4445 } 4446 if (strncmp (input_line_pointer, "\"data1\"", 7) == 0) 4447 { 4448 input_line_pointer += 7; 4449 s_data1 (); 4450 return; 4451 } 4452 if (strncmp (input_line_pointer, "\"bss\"", 5) == 0) 4453 { 4454 input_line_pointer += 5; 4455 /* We only support 2 segments -- text and data -- for now, so 4456 things in the "bss segment" will have to go into data for now. 4457 You can still allocate SEG_BSS stuff with .lcomm or .reserve. */ 4458 subseg_set (data_section, 255); /* FIXME-SOMEDAY. */ 4459 return; 4460 } 4461 as_bad (_("Unknown segment type")); 4462 demand_empty_rest_of_line (); 4463 } 4464 4465 static void 4466 s_data1 (void) 4467 { 4468 subseg_set (data_section, 1); 4469 demand_empty_rest_of_line (); 4470 } 4471 4472 static void 4473 s_proc (int ignore ATTRIBUTE_UNUSED) 4474 { 4475 while (!is_end_of_line[(unsigned char) *input_line_pointer]) 4476 { 4477 ++input_line_pointer; 4478 } 4479 ++input_line_pointer; 4480 } 4481 4482 /* This static variable is set by s_uacons to tell sparc_cons_align 4483 that the expression does not need to be aligned. */ 4484 4485 static int sparc_no_align_cons = 0; 4486 4487 /* This handles the unaligned space allocation pseudo-ops, such as 4488 .uaword. .uaword is just like .word, but the value does not need 4489 to be aligned. */ 4490 4491 static void 4492 s_uacons (int bytes) 4493 { 4494 /* Tell sparc_cons_align not to align this value. */ 4495 sparc_no_align_cons = 1; 4496 cons (bytes); 4497 sparc_no_align_cons = 0; 4498 } 4499 4500 /* This handles the native word allocation pseudo-op .nword. 4501 For sparc_arch_size 32 it is equivalent to .word, for 4502 sparc_arch_size 64 it is equivalent to .xword. */ 4503 4504 static void 4505 s_ncons (int bytes ATTRIBUTE_UNUSED) 4506 { 4507 cons (sparc_arch_size == 32 ? 4 : 8); 4508 } 4509 4510 #ifdef OBJ_ELF 4511 /* Handle the SPARC ELF .register pseudo-op. This sets the binding of a 4512 global register. 4513 The syntax is: 4514 4515 .register %g[2367],{#scratch|symbolname|#ignore} 4516 */ 4517 4518 static void 4519 s_register (int ignore ATTRIBUTE_UNUSED) 4520 { 4521 char c; 4522 int reg; 4523 int flags; 4524 char *regname; 4525 4526 if (input_line_pointer[0] != '%' 4527 || input_line_pointer[1] != 'g' 4528 || ((input_line_pointer[2] & ~1) != '2' 4529 && (input_line_pointer[2] & ~1) != '6') 4530 || input_line_pointer[3] != ',') 4531 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4532 reg = input_line_pointer[2] - '0'; 4533 input_line_pointer += 4; 4534 4535 if (*input_line_pointer == '#') 4536 { 4537 ++input_line_pointer; 4538 c = get_symbol_name (®name); 4539 if (strcmp (regname, "scratch") && strcmp (regname, "ignore")) 4540 as_bad (_("register syntax is .register %%g[2367],{#scratch|symbolname|#ignore}")); 4541 if (regname[0] == 'i') 4542 regname = NULL; 4543 else 4544 regname = (char *) ""; 4545 } 4546 else 4547 { 4548 c = get_symbol_name (®name); 4549 } 4550 4551 if (sparc_arch_size == 64) 4552 { 4553 if (globals[reg]) 4554 { 4555 if ((regname && globals[reg] != (symbolS *) 1 4556 && strcmp (S_GET_NAME (globals[reg]), regname)) 4557 || ((regname != NULL) ^ (globals[reg] != (symbolS *) 1))) 4558 as_bad (_("redefinition of global register")); 4559 } 4560 else 4561 { 4562 if (regname == NULL) 4563 globals[reg] = (symbolS *) 1; 4564 else 4565 { 4566 if (*regname) 4567 { 4568 if (symbol_find (regname)) 4569 as_bad (_("Register symbol %s already defined."), 4570 regname); 4571 } 4572 globals[reg] = symbol_make (regname); 4573 flags = symbol_get_bfdsym (globals[reg])->flags; 4574 if (! *regname) 4575 flags = flags & ~(BSF_GLOBAL|BSF_LOCAL|BSF_WEAK); 4576 if (! (flags & (BSF_GLOBAL|BSF_LOCAL|BSF_WEAK))) 4577 flags |= BSF_GLOBAL; 4578 symbol_get_bfdsym (globals[reg])->flags = flags; 4579 S_SET_VALUE (globals[reg], (valueT) reg); 4580 S_SET_ALIGN (globals[reg], reg); 4581 S_SET_SIZE (globals[reg], 0); 4582 /* Although we actually want undefined_section here, 4583 we have to use absolute_section, because otherwise 4584 generic as code will make it a COM section. 4585 We fix this up in sparc_adjust_symtab. */ 4586 S_SET_SEGMENT (globals[reg], absolute_section); 4587 S_SET_OTHER (globals[reg], 0); 4588 elf_symbol (symbol_get_bfdsym (globals[reg])) 4589 ->internal_elf_sym.st_info = 4590 ELF_ST_INFO(STB_GLOBAL, STT_REGISTER); 4591 elf_symbol (symbol_get_bfdsym (globals[reg])) 4592 ->internal_elf_sym.st_shndx = SHN_UNDEF; 4593 } 4594 } 4595 } 4596 4597 (void) restore_line_pointer (c); 4598 4599 demand_empty_rest_of_line (); 4600 } 4601 4602 /* Adjust the symbol table. We set undefined sections for STT_REGISTER 4603 symbols which need it. */ 4604 4605 void 4606 sparc_adjust_symtab (void) 4607 { 4608 symbolS *sym; 4609 4610 for (sym = symbol_rootP; sym != NULL; sym = symbol_next (sym)) 4611 { 4612 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4613 ->internal_elf_sym.st_info) != STT_REGISTER) 4614 continue; 4615 4616 if (ELF_ST_TYPE (elf_symbol (symbol_get_bfdsym (sym)) 4617 ->internal_elf_sym.st_shndx != SHN_UNDEF)) 4618 continue; 4619 4620 S_SET_SEGMENT (sym, undefined_section); 4621 } 4622 } 4623 #endif 4624 4625 /* If the --enforce-aligned-data option is used, we require .word, 4626 et. al., to be aligned correctly. We do it by setting up an 4627 rs_align_code frag, and checking in HANDLE_ALIGN to make sure that 4628 no unexpected alignment was introduced. 4629 4630 The SunOS and Solaris native assemblers enforce aligned data by 4631 default. We don't want to do that, because gcc can deliberately 4632 generate misaligned data if the packed attribute is used. Instead, 4633 we permit misaligned data by default, and permit the user to set an 4634 option to check for it. */ 4635 4636 void 4637 sparc_cons_align (int nbytes) 4638 { 4639 int nalign; 4640 4641 /* Only do this if we are enforcing aligned data. */ 4642 if (! enforce_aligned_data) 4643 return; 4644 4645 /* Don't align if this is an unaligned pseudo-op. */ 4646 if (sparc_no_align_cons) 4647 return; 4648 4649 nalign = mylog2 (nbytes); 4650 if (nalign == 0) 4651 return; 4652 4653 gas_assert (nalign > 0); 4654 4655 if (now_seg == absolute_section) 4656 { 4657 if ((abs_section_offset & ((1 << nalign) - 1)) != 0) 4658 as_bad (_("misaligned data")); 4659 return; 4660 } 4661 4662 frag_var (rs_align_test, 1, 1, (relax_substateT) 0, 4663 (symbolS *) NULL, (offsetT) nalign, (char *) NULL); 4664 4665 record_alignment (now_seg, nalign); 4666 } 4667 4668 /* This is called from HANDLE_ALIGN in tc-sparc.h. */ 4669 4670 void 4671 sparc_handle_align (fragS *fragp) 4672 { 4673 int count, fix; 4674 char *p; 4675 4676 count = fragp->fr_next->fr_address - fragp->fr_address - fragp->fr_fix; 4677 4678 switch (fragp->fr_type) 4679 { 4680 case rs_align_test: 4681 if (count != 0) 4682 as_bad_where (fragp->fr_file, fragp->fr_line, _("misaligned data")); 4683 break; 4684 4685 case rs_align_code: 4686 p = fragp->fr_literal + fragp->fr_fix; 4687 fix = 0; 4688 4689 if (count & 3) 4690 { 4691 fix = count & 3; 4692 memset (p, 0, fix); 4693 p += fix; 4694 count -= fix; 4695 } 4696 4697 if (SPARC_OPCODE_ARCH_V9_P (max_architecture) && count > 8) 4698 { 4699 unsigned wval = (0x30680000 | count >> 2); /* ba,a,pt %xcc, 1f */ 4700 if (INSN_BIG_ENDIAN) 4701 number_to_chars_bigendian (p, wval, 4); 4702 else 4703 number_to_chars_littleendian (p, wval, 4); 4704 p += 4; 4705 count -= 4; 4706 fix += 4; 4707 } 4708 4709 if (INSN_BIG_ENDIAN) 4710 number_to_chars_bigendian (p, 0x01000000, 4); 4711 else 4712 number_to_chars_littleendian (p, 0x01000000, 4); 4713 4714 fragp->fr_fix += fix; 4715 fragp->fr_var = 4; 4716 break; 4717 4718 default: 4719 break; 4720 } 4721 } 4722 4723 #ifdef OBJ_ELF 4724 /* Some special processing for a Sparc ELF file. */ 4725 4726 void 4727 sparc_elf_final_processing (void) 4728 { 4729 /* Set the Sparc ELF flag bits. FIXME: There should probably be some 4730 sort of BFD interface for this. */ 4731 if (sparc_arch_size == 64) 4732 { 4733 switch (sparc_memory_model) 4734 { 4735 case MM_RMO: 4736 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_RMO; 4737 break; 4738 case MM_PSO: 4739 elf_elfheader (stdoutput)->e_flags |= EF_SPARCV9_PSO; 4740 break; 4741 default: 4742 break; 4743 } 4744 } 4745 else if (current_architecture >= SPARC_OPCODE_ARCH_V9) 4746 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_32PLUS; 4747 if (current_architecture == SPARC_OPCODE_ARCH_V9A) 4748 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1; 4749 else if (current_architecture == SPARC_OPCODE_ARCH_V9B) 4750 elf_elfheader (stdoutput)->e_flags |= EF_SPARC_SUN_US1|EF_SPARC_SUN_US3; 4751 } 4752 4753 const char * 4754 sparc_cons (expressionS *exp, int size) 4755 { 4756 char *save; 4757 const char *sparc_cons_special_reloc = NULL; 4758 4759 SKIP_WHITESPACE (); 4760 save = input_line_pointer; 4761 if (input_line_pointer[0] == '%' 4762 && input_line_pointer[1] == 'r' 4763 && input_line_pointer[2] == '_') 4764 { 4765 if (strncmp (input_line_pointer + 3, "disp", 4) == 0) 4766 { 4767 input_line_pointer += 7; 4768 sparc_cons_special_reloc = "disp"; 4769 } 4770 else if (strncmp (input_line_pointer + 3, "plt", 3) == 0) 4771 { 4772 if (size != 4 && size != 8) 4773 as_bad (_("Illegal operands: %%r_plt in %d-byte data field"), size); 4774 else 4775 { 4776 input_line_pointer += 6; 4777 sparc_cons_special_reloc = "plt"; 4778 } 4779 } 4780 else if (strncmp (input_line_pointer + 3, "tls_dtpoff", 10) == 0) 4781 { 4782 if (size != 4 && size != 8) 4783 as_bad (_("Illegal operands: %%r_tls_dtpoff in %d-byte data field"), size); 4784 else 4785 { 4786 input_line_pointer += 13; 4787 sparc_cons_special_reloc = "tls_dtpoff"; 4788 } 4789 } 4790 if (sparc_cons_special_reloc) 4791 { 4792 int bad = 0; 4793 4794 switch (size) 4795 { 4796 case 1: 4797 if (*input_line_pointer != '8') 4798 bad = 1; 4799 input_line_pointer--; 4800 break; 4801 case 2: 4802 if (input_line_pointer[0] != '1' || input_line_pointer[1] != '6') 4803 bad = 1; 4804 break; 4805 case 4: 4806 if (input_line_pointer[0] != '3' || input_line_pointer[1] != '2') 4807 bad = 1; 4808 break; 4809 case 8: 4810 if (input_line_pointer[0] != '6' || input_line_pointer[1] != '4') 4811 bad = 1; 4812 break; 4813 default: 4814 bad = 1; 4815 break; 4816 } 4817 4818 if (bad) 4819 { 4820 as_bad (_("Illegal operands: Only %%r_%s%d allowed in %d-byte data fields"), 4821 sparc_cons_special_reloc, size * 8, size); 4822 } 4823 else 4824 { 4825 input_line_pointer += 2; 4826 if (*input_line_pointer != '(') 4827 { 4828 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4829 sparc_cons_special_reloc, size * 8); 4830 bad = 1; 4831 } 4832 } 4833 4834 if (bad) 4835 { 4836 input_line_pointer = save; 4837 sparc_cons_special_reloc = NULL; 4838 } 4839 else 4840 { 4841 int c; 4842 char *end = ++input_line_pointer; 4843 int npar = 0; 4844 4845 while (! is_end_of_line[(c = *end)]) 4846 { 4847 if (c == '(') 4848 npar++; 4849 else if (c == ')') 4850 { 4851 if (!npar) 4852 break; 4853 npar--; 4854 } 4855 end++; 4856 } 4857 4858 if (c != ')') 4859 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4860 sparc_cons_special_reloc, size * 8); 4861 else 4862 { 4863 *end = '\0'; 4864 expression (exp); 4865 *end = c; 4866 if (input_line_pointer != end) 4867 { 4868 as_bad (_("Illegal operands: %%r_%s%d requires arguments in ()"), 4869 sparc_cons_special_reloc, size * 8); 4870 } 4871 else 4872 { 4873 input_line_pointer++; 4874 SKIP_WHITESPACE (); 4875 c = *input_line_pointer; 4876 if (! is_end_of_line[c] && c != ',') 4877 as_bad (_("Illegal operands: garbage after %%r_%s%d()"), 4878 sparc_cons_special_reloc, size * 8); 4879 } 4880 } 4881 } 4882 } 4883 } 4884 if (sparc_cons_special_reloc == NULL) 4885 expression (exp); 4886 return sparc_cons_special_reloc; 4887 } 4888 4889 #endif 4890 4891 /* This is called by emit_expr via TC_CONS_FIX_NEW when creating a 4892 reloc for a cons. We could use the definition there, except that 4893 we want to handle little endian relocs specially. */ 4894 4895 void 4896 cons_fix_new_sparc (fragS *frag, 4897 int where, 4898 unsigned int nbytes, 4899 expressionS *exp, 4900 const char *sparc_cons_special_reloc) 4901 { 4902 bfd_reloc_code_real_type r; 4903 4904 r = (nbytes == 1 ? BFD_RELOC_8 : 4905 (nbytes == 2 ? BFD_RELOC_16 : 4906 (nbytes == 4 ? BFD_RELOC_32 : BFD_RELOC_64))); 4907 4908 if (target_little_endian_data 4909 && nbytes == 4 4910 && now_seg->flags & SEC_ALLOC) 4911 r = BFD_RELOC_SPARC_REV32; 4912 4913 if (sparc_cons_special_reloc) 4914 { 4915 if (*sparc_cons_special_reloc == 'd') 4916 switch (nbytes) 4917 { 4918 case 1: r = BFD_RELOC_8_PCREL; break; 4919 case 2: r = BFD_RELOC_16_PCREL; break; 4920 case 4: r = BFD_RELOC_32_PCREL; break; 4921 case 8: r = BFD_RELOC_64_PCREL; break; 4922 default: abort (); 4923 } 4924 else if (*sparc_cons_special_reloc == 'p') 4925 switch (nbytes) 4926 { 4927 case 4: r = BFD_RELOC_SPARC_PLT32; break; 4928 case 8: r = BFD_RELOC_SPARC_PLT64; break; 4929 } 4930 else 4931 switch (nbytes) 4932 { 4933 case 4: r = BFD_RELOC_SPARC_TLS_DTPOFF32; break; 4934 case 8: r = BFD_RELOC_SPARC_TLS_DTPOFF64; break; 4935 } 4936 } 4937 else if (sparc_no_align_cons) 4938 { 4939 switch (nbytes) 4940 { 4941 case 2: r = BFD_RELOC_SPARC_UA16; break; 4942 case 4: r = BFD_RELOC_SPARC_UA32; break; 4943 case 8: r = BFD_RELOC_SPARC_UA64; break; 4944 default: abort (); 4945 } 4946 } 4947 4948 fix_new_exp (frag, where, (int) nbytes, exp, 0, r); 4949 } 4950 4951 void 4952 sparc_cfi_frame_initial_instructions (void) 4953 { 4954 cfi_add_CFA_def_cfa (14, sparc_arch_size == 64 ? 0x7ff : 0); 4955 } 4956 4957 int 4958 sparc_regname_to_dw2regnum (char *regname) 4959 { 4960 char *q; 4961 int i; 4962 4963 if (!regname[0]) 4964 return -1; 4965 4966 switch (regname[0]) 4967 { 4968 case 'g': i = 0; break; 4969 case 'o': i = 1; break; 4970 case 'l': i = 2; break; 4971 case 'i': i = 3; break; 4972 default: i = -1; break; 4973 } 4974 if (i != -1) 4975 { 4976 if (regname[1] < '0' || regname[1] > '8' || regname[2]) 4977 return -1; 4978 return i * 8 + regname[1] - '0'; 4979 } 4980 if (regname[0] == 's' && regname[1] == 'p' && !regname[2]) 4981 return 14; 4982 if (regname[0] == 'f' && regname[1] == 'p' && !regname[2]) 4983 return 30; 4984 if (regname[0] == 'f' || regname[0] == 'r') 4985 { 4986 unsigned int regnum; 4987 4988 regnum = strtoul (regname + 1, &q, 10); 4989 if (q == NULL || *q) 4990 return -1; 4991 if (regnum >= ((regname[0] == 'f' 4992 && SPARC_OPCODE_ARCH_V9_P (max_architecture)) 4993 ? 64 : 32)) 4994 return -1; 4995 if (regname[0] == 'f') 4996 { 4997 regnum += 32; 4998 if (regnum >= 64 && (regnum & 1)) 4999 return -1; 5000 } 5001 return regnum; 5002 } 5003 return -1; 5004 } 5005 5006 void 5007 sparc_cfi_emit_pcrel_expr (expressionS *exp, unsigned int nbytes) 5008 { 5009 sparc_no_align_cons = 1; 5010 emit_expr_with_reloc (exp, nbytes, "disp"); 5011 sparc_no_align_cons = 0; 5012 } 5013
