1 /* 2 * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #include <arch_helpers.h> 8 #include <assert.h> 9 #include <debug.h> 10 #include <platform.h> 11 #include <platform_def.h> 12 #include <tsp.h> 13 #include "tsp_private.h" 14 15 /******************************************************************************* 16 * This function updates the TSP statistics for S-EL1 interrupts handled 17 * synchronously i.e the ones that have been handed over by the TSPD. It also 18 * keeps count of the number of times control was passed back to the TSPD 19 * after handling the interrupt. In the future it will be possible that the 20 * TSPD hands over an S-EL1 interrupt to the TSP but does not expect it to 21 * return execution. This statistic will be useful to distinguish between these 22 * two models of synchronous S-EL1 interrupt handling. The 'elr_el3' parameter 23 * contains the address of the instruction in normal world where this S-EL1 24 * interrupt was generated. 25 ******************************************************************************/ 26 void tsp_update_sync_sel1_intr_stats(uint32_t type, uint64_t elr_el3) 27 { 28 uint32_t linear_id = plat_my_core_pos(); 29 30 tsp_stats[linear_id].sync_sel1_intr_count++; 31 if (type == TSP_HANDLE_SEL1_INTR_AND_RETURN) 32 tsp_stats[linear_id].sync_sel1_intr_ret_count++; 33 34 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 35 spin_lock(&console_lock); 36 VERBOSE("TSP: cpu 0x%lx sync s-el1 interrupt request from 0x%lx\n", 37 read_mpidr(), elr_el3); 38 VERBOSE("TSP: cpu 0x%lx: %d sync s-el1 interrupt requests," 39 " %d sync s-el1 interrupt returns\n", 40 read_mpidr(), 41 tsp_stats[linear_id].sync_sel1_intr_count, 42 tsp_stats[linear_id].sync_sel1_intr_ret_count); 43 spin_unlock(&console_lock); 44 #endif 45 } 46 47 /****************************************************************************** 48 * This function is invoked when a non S-EL1 interrupt is received and causes 49 * the preemption of TSP. This function returns TSP_PREEMPTED and results 50 * in the control being handed over to EL3 for handling the interrupt. 51 *****************************************************************************/ 52 int32_t tsp_handle_preemption(void) 53 { 54 uint32_t linear_id = plat_my_core_pos(); 55 56 tsp_stats[linear_id].preempt_intr_count++; 57 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 58 spin_lock(&console_lock); 59 VERBOSE("TSP: cpu 0x%lx: %d preempt interrupt requests\n", 60 read_mpidr(), tsp_stats[linear_id].preempt_intr_count); 61 spin_unlock(&console_lock); 62 #endif 63 return TSP_PREEMPTED; 64 } 65 66 /******************************************************************************* 67 * TSP interrupt handler is called as a part of both synchronous and 68 * asynchronous handling of TSP interrupts. Currently the physical timer 69 * interrupt is the only S-EL1 interrupt that this handler expects. It returns 70 * 0 upon successfully handling the expected interrupt and all other 71 * interrupts are treated as normal world or EL3 interrupts. 72 ******************************************************************************/ 73 int32_t tsp_common_int_handler(void) 74 { 75 uint32_t linear_id = plat_my_core_pos(), id; 76 77 /* 78 * Get the highest priority pending interrupt id and see if it is the 79 * secure physical generic timer interrupt in which case, handle it. 80 * Otherwise throw this interrupt at the EL3 firmware. 81 * 82 * There is a small time window between reading the highest priority 83 * pending interrupt and acknowledging it during which another 84 * interrupt of higher priority could become the highest pending 85 * interrupt. This is not expected to happen currently for TSP. 86 */ 87 id = plat_ic_get_pending_interrupt_id(); 88 89 /* TSP can only handle the secure physical timer interrupt */ 90 if (id != TSP_IRQ_SEC_PHY_TIMER) 91 return tsp_handle_preemption(); 92 93 /* 94 * Acknowledge and handle the secure timer interrupt. Also sanity check 95 * if it has been preempted by another interrupt through an assertion. 96 */ 97 id = plat_ic_acknowledge_interrupt(); 98 assert(id == TSP_IRQ_SEC_PHY_TIMER); 99 tsp_generic_timer_handler(); 100 plat_ic_end_of_interrupt(id); 101 102 /* Update the statistics and print some messages */ 103 tsp_stats[linear_id].sel1_intr_count++; 104 #if LOG_LEVEL >= LOG_LEVEL_VERBOSE 105 spin_lock(&console_lock); 106 VERBOSE("TSP: cpu 0x%lx handled S-EL1 interrupt %d\n", 107 read_mpidr(), id); 108 VERBOSE("TSP: cpu 0x%lx: %d S-EL1 requests\n", 109 read_mpidr(), tsp_stats[linear_id].sel1_intr_count); 110 spin_unlock(&console_lock); 111 #endif 112 return 0; 113 } 114
