1 // Copyright 2013 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ 6 #define V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ 7 8 #include <vector> 9 10 #include "src/arm64/assembler-arm64.h" 11 #include "src/bailout-reason.h" 12 #include "src/base/bits.h" 13 #include "src/globals.h" 14 15 // Simulator specific helpers. 16 #if USE_SIMULATOR 17 // TODO(all): If possible automatically prepend an indicator like 18 // UNIMPLEMENTED or LOCATION. 19 #define ASM_UNIMPLEMENTED(message) \ 20 __ Debug(message, __LINE__, NO_PARAM) 21 #define ASM_UNIMPLEMENTED_BREAK(message) \ 22 __ Debug(message, __LINE__, \ 23 FLAG_ignore_asm_unimplemented_break ? NO_PARAM : BREAK) 24 #if DEBUG 25 #define ASM_LOCATION(message) __ Debug("LOCATION: " message, __LINE__, NO_PARAM) 26 #else 27 #define ASM_LOCATION(message) 28 #endif 29 #else 30 #define ASM_UNIMPLEMENTED(message) 31 #define ASM_UNIMPLEMENTED_BREAK(message) 32 #define ASM_LOCATION(message) 33 #endif 34 35 36 namespace v8 { 37 namespace internal { 38 39 // Give alias names to registers for calling conventions. 40 #define kReturnRegister0 x0 41 #define kReturnRegister1 x1 42 #define kReturnRegister2 x2 43 #define kJSFunctionRegister x1 44 #define kContextRegister cp 45 #define kAllocateSizeRegister x1 46 #define kInterpreterAccumulatorRegister x0 47 #define kInterpreterBytecodeOffsetRegister x19 48 #define kInterpreterBytecodeArrayRegister x20 49 #define kInterpreterDispatchTableRegister x21 50 #define kJavaScriptCallArgCountRegister x0 51 #define kJavaScriptCallNewTargetRegister x3 52 #define kRuntimeCallFunctionRegister x1 53 #define kRuntimeCallArgCountRegister x0 54 55 #define LS_MACRO_LIST(V) \ 56 V(Ldrb, Register&, rt, LDRB_w) \ 57 V(Strb, Register&, rt, STRB_w) \ 58 V(Ldrsb, Register&, rt, rt.Is64Bits() ? LDRSB_x : LDRSB_w) \ 59 V(Ldrh, Register&, rt, LDRH_w) \ 60 V(Strh, Register&, rt, STRH_w) \ 61 V(Ldrsh, Register&, rt, rt.Is64Bits() ? LDRSH_x : LDRSH_w) \ 62 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \ 63 V(Str, CPURegister&, rt, StoreOpFor(rt)) \ 64 V(Ldrsw, Register&, rt, LDRSW_x) 65 66 #define LSPAIR_MACRO_LIST(V) \ 67 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \ 68 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \ 69 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x) 70 71 #define LDA_STL_MACRO_LIST(V) \ 72 V(Ldarb, ldarb) \ 73 V(Ldarh, ldarh) \ 74 V(Ldar, ldar) \ 75 V(Ldaxrb, ldaxrb) \ 76 V(Ldaxrh, ldaxrh) \ 77 V(Ldaxr, ldaxr) \ 78 V(Stlrb, stlrb) \ 79 V(Stlrh, stlrh) \ 80 V(Stlr, stlr) 81 82 #define STLX_MACRO_LIST(V) \ 83 V(Stlxrb, stlxrb) \ 84 V(Stlxrh, stlxrh) \ 85 V(Stlxr, stlxr) 86 87 // ---------------------------------------------------------------------------- 88 // Static helper functions 89 90 // Generate a MemOperand for loading a field from an object. 91 inline MemOperand FieldMemOperand(Register object, int offset); 92 inline MemOperand UntagSmiFieldMemOperand(Register object, int offset); 93 94 // Generate a MemOperand for loading a SMI from memory. 95 inline MemOperand UntagSmiMemOperand(Register object, int offset); 96 97 98 // ---------------------------------------------------------------------------- 99 // MacroAssembler 100 101 enum BranchType { 102 // Copies of architectural conditions. 103 // The associated conditions can be used in place of those, the code will 104 // take care of reinterpreting them with the correct type. 105 integer_eq = eq, 106 integer_ne = ne, 107 integer_hs = hs, 108 integer_lo = lo, 109 integer_mi = mi, 110 integer_pl = pl, 111 integer_vs = vs, 112 integer_vc = vc, 113 integer_hi = hi, 114 integer_ls = ls, 115 integer_ge = ge, 116 integer_lt = lt, 117 integer_gt = gt, 118 integer_le = le, 119 integer_al = al, 120 integer_nv = nv, 121 122 // These two are *different* from the architectural codes al and nv. 123 // 'always' is used to generate unconditional branches. 124 // 'never' is used to not generate a branch (generally as the inverse 125 // branch type of 'always). 126 always, never, 127 // cbz and cbnz 128 reg_zero, reg_not_zero, 129 // tbz and tbnz 130 reg_bit_clear, reg_bit_set, 131 132 // Aliases. 133 kBranchTypeFirstCondition = eq, 134 kBranchTypeLastCondition = nv, 135 kBranchTypeFirstUsingReg = reg_zero, 136 kBranchTypeFirstUsingBit = reg_bit_clear 137 }; 138 139 inline BranchType InvertBranchType(BranchType type) { 140 if (kBranchTypeFirstCondition <= type && type <= kBranchTypeLastCondition) { 141 return static_cast<BranchType>( 142 NegateCondition(static_cast<Condition>(type))); 143 } else { 144 return static_cast<BranchType>(type ^ 1); 145 } 146 } 147 148 enum RememberedSetAction { EMIT_REMEMBERED_SET, OMIT_REMEMBERED_SET }; 149 enum SmiCheck { INLINE_SMI_CHECK, OMIT_SMI_CHECK }; 150 enum PointersToHereCheck { 151 kPointersToHereMaybeInteresting, 152 kPointersToHereAreAlwaysInteresting 153 }; 154 enum LinkRegisterStatus { kLRHasNotBeenSaved, kLRHasBeenSaved }; 155 enum TargetAddressStorageMode { 156 CAN_INLINE_TARGET_ADDRESS, 157 NEVER_INLINE_TARGET_ADDRESS 158 }; 159 enum UntagMode { kNotSpeculativeUntag, kSpeculativeUntag }; 160 enum ArrayHasHoles { kArrayCantHaveHoles, kArrayCanHaveHoles }; 161 enum CopyHint { kCopyUnknown, kCopyShort, kCopyLong }; 162 enum DiscardMoveMode { kDontDiscardForSameWReg, kDiscardForSameWReg }; 163 enum SeqStringSetCharCheckIndexType { kIndexIsSmi, kIndexIsInteger32 }; 164 165 class MacroAssembler : public Assembler { 166 public: 167 MacroAssembler(Isolate* isolate, byte* buffer, unsigned buffer_size, 168 CodeObjectRequired create_code_object); 169 170 inline Handle<Object> CodeObject(); 171 172 // Instruction set functions ------------------------------------------------ 173 // Logical macros. 174 inline void And(const Register& rd, 175 const Register& rn, 176 const Operand& operand); 177 inline void Ands(const Register& rd, 178 const Register& rn, 179 const Operand& operand); 180 inline void Bic(const Register& rd, 181 const Register& rn, 182 const Operand& operand); 183 inline void Bics(const Register& rd, 184 const Register& rn, 185 const Operand& operand); 186 inline void Orr(const Register& rd, 187 const Register& rn, 188 const Operand& operand); 189 inline void Orn(const Register& rd, 190 const Register& rn, 191 const Operand& operand); 192 inline void Eor(const Register& rd, 193 const Register& rn, 194 const Operand& operand); 195 inline void Eon(const Register& rd, 196 const Register& rn, 197 const Operand& operand); 198 inline void Tst(const Register& rn, const Operand& operand); 199 void LogicalMacro(const Register& rd, 200 const Register& rn, 201 const Operand& operand, 202 LogicalOp op); 203 204 // Add and sub macros. 205 inline void Add(const Register& rd, 206 const Register& rn, 207 const Operand& operand); 208 inline void Adds(const Register& rd, 209 const Register& rn, 210 const Operand& operand); 211 inline void Sub(const Register& rd, 212 const Register& rn, 213 const Operand& operand); 214 inline void Subs(const Register& rd, 215 const Register& rn, 216 const Operand& operand); 217 inline void Cmn(const Register& rn, const Operand& operand); 218 inline void Cmp(const Register& rn, const Operand& operand); 219 inline void Neg(const Register& rd, 220 const Operand& operand); 221 inline void Negs(const Register& rd, 222 const Operand& operand); 223 224 void AddSubMacro(const Register& rd, 225 const Register& rn, 226 const Operand& operand, 227 FlagsUpdate S, 228 AddSubOp op); 229 230 // Add/sub with carry macros. 231 inline void Adc(const Register& rd, 232 const Register& rn, 233 const Operand& operand); 234 inline void Adcs(const Register& rd, 235 const Register& rn, 236 const Operand& operand); 237 inline void Sbc(const Register& rd, 238 const Register& rn, 239 const Operand& operand); 240 inline void Sbcs(const Register& rd, 241 const Register& rn, 242 const Operand& operand); 243 inline void Ngc(const Register& rd, 244 const Operand& operand); 245 inline void Ngcs(const Register& rd, 246 const Operand& operand); 247 void AddSubWithCarryMacro(const Register& rd, 248 const Register& rn, 249 const Operand& operand, 250 FlagsUpdate S, 251 AddSubWithCarryOp op); 252 253 // Move macros. 254 void Mov(const Register& rd, 255 const Operand& operand, 256 DiscardMoveMode discard_mode = kDontDiscardForSameWReg); 257 void Mov(const Register& rd, uint64_t imm); 258 inline void Mvn(const Register& rd, uint64_t imm); 259 void Mvn(const Register& rd, const Operand& operand); 260 static bool IsImmMovn(uint64_t imm, unsigned reg_size); 261 static bool IsImmMovz(uint64_t imm, unsigned reg_size); 262 static unsigned CountClearHalfWords(uint64_t imm, unsigned reg_size); 263 264 // Try to move an immediate into the destination register in a single 265 // instruction. Returns true for success, and updates the contents of dst. 266 // Returns false, otherwise. 267 bool TryOneInstrMoveImmediate(const Register& dst, int64_t imm); 268 269 // Move an immediate into register dst, and return an Operand object for use 270 // with a subsequent instruction that accepts a shift. The value moved into 271 // dst is not necessarily equal to imm; it may have had a shifting operation 272 // applied to it that will be subsequently undone by the shift applied in the 273 // Operand. 274 Operand MoveImmediateForShiftedOp(const Register& dst, int64_t imm); 275 276 // Conditional macros. 277 inline void Ccmp(const Register& rn, 278 const Operand& operand, 279 StatusFlags nzcv, 280 Condition cond); 281 inline void Ccmn(const Register& rn, 282 const Operand& operand, 283 StatusFlags nzcv, 284 Condition cond); 285 void ConditionalCompareMacro(const Register& rn, 286 const Operand& operand, 287 StatusFlags nzcv, 288 Condition cond, 289 ConditionalCompareOp op); 290 void Csel(const Register& rd, 291 const Register& rn, 292 const Operand& operand, 293 Condition cond); 294 295 // Load/store macros. 296 #define DECLARE_FUNCTION(FN, REGTYPE, REG, OP) \ 297 inline void FN(const REGTYPE REG, const MemOperand& addr); 298 LS_MACRO_LIST(DECLARE_FUNCTION) 299 #undef DECLARE_FUNCTION 300 301 void LoadStoreMacro(const CPURegister& rt, 302 const MemOperand& addr, 303 LoadStoreOp op); 304 305 #define DECLARE_FUNCTION(FN, REGTYPE, REG, REG2, OP) \ 306 inline void FN(const REGTYPE REG, const REGTYPE REG2, const MemOperand& addr); 307 LSPAIR_MACRO_LIST(DECLARE_FUNCTION) 308 #undef DECLARE_FUNCTION 309 310 void LoadStorePairMacro(const CPURegister& rt, const CPURegister& rt2, 311 const MemOperand& addr, LoadStorePairOp op); 312 313 // Load-acquire/store-release macros. 314 #define DECLARE_FUNCTION(FN, OP) \ 315 inline void FN(const Register& rt, const Register& rn); 316 LDA_STL_MACRO_LIST(DECLARE_FUNCTION) 317 #undef DECLARE_FUNCTION 318 319 #define DECLARE_FUNCTION(FN, OP) \ 320 inline void FN(const Register& rs, const Register& rt, const Register& rn); 321 STLX_MACRO_LIST(DECLARE_FUNCTION) 322 #undef DECLARE_FUNCTION 323 324 // V8-specific load/store helpers. 325 void Load(const Register& rt, const MemOperand& addr, Representation r); 326 void Store(const Register& rt, const MemOperand& addr, Representation r); 327 328 enum AdrHint { 329 // The target must be within the immediate range of adr. 330 kAdrNear, 331 // The target may be outside of the immediate range of adr. Additional 332 // instructions may be emitted. 333 kAdrFar 334 }; 335 void Adr(const Register& rd, Label* label, AdrHint = kAdrNear); 336 337 // Remaining instructions are simple pass-through calls to the assembler. 338 inline void Asr(const Register& rd, const Register& rn, unsigned shift); 339 inline void Asr(const Register& rd, const Register& rn, const Register& rm); 340 341 // Branch type inversion relies on these relations. 342 STATIC_ASSERT((reg_zero == (reg_not_zero ^ 1)) && 343 (reg_bit_clear == (reg_bit_set ^ 1)) && 344 (always == (never ^ 1))); 345 346 void B(Label* label, BranchType type, Register reg = NoReg, int bit = -1); 347 348 inline void B(Label* label); 349 inline void B(Condition cond, Label* label); 350 void B(Label* label, Condition cond); 351 inline void Bfi(const Register& rd, 352 const Register& rn, 353 unsigned lsb, 354 unsigned width); 355 inline void Bfxil(const Register& rd, 356 const Register& rn, 357 unsigned lsb, 358 unsigned width); 359 inline void Bind(Label* label); 360 inline void Bl(Label* label); 361 inline void Blr(const Register& xn); 362 inline void Br(const Register& xn); 363 inline void Brk(int code); 364 void Cbnz(const Register& rt, Label* label); 365 void Cbz(const Register& rt, Label* label); 366 inline void Cinc(const Register& rd, const Register& rn, Condition cond); 367 inline void Cinv(const Register& rd, const Register& rn, Condition cond); 368 inline void Cls(const Register& rd, const Register& rn); 369 inline void Clz(const Register& rd, const Register& rn); 370 inline void Cneg(const Register& rd, const Register& rn, Condition cond); 371 inline void CzeroX(const Register& rd, Condition cond); 372 inline void CmovX(const Register& rd, const Register& rn, Condition cond); 373 inline void Cset(const Register& rd, Condition cond); 374 inline void Csetm(const Register& rd, Condition cond); 375 inline void Csinc(const Register& rd, 376 const Register& rn, 377 const Register& rm, 378 Condition cond); 379 inline void Csinv(const Register& rd, 380 const Register& rn, 381 const Register& rm, 382 Condition cond); 383 inline void Csneg(const Register& rd, 384 const Register& rn, 385 const Register& rm, 386 Condition cond); 387 inline void Dmb(BarrierDomain domain, BarrierType type); 388 inline void Dsb(BarrierDomain domain, BarrierType type); 389 inline void Debug(const char* message, uint32_t code, Instr params = BREAK); 390 inline void Extr(const Register& rd, 391 const Register& rn, 392 const Register& rm, 393 unsigned lsb); 394 inline void Fabs(const FPRegister& fd, const FPRegister& fn); 395 inline void Fadd(const FPRegister& fd, 396 const FPRegister& fn, 397 const FPRegister& fm); 398 inline void Fccmp(const FPRegister& fn, 399 const FPRegister& fm, 400 StatusFlags nzcv, 401 Condition cond); 402 inline void Fcmp(const FPRegister& fn, const FPRegister& fm); 403 inline void Fcmp(const FPRegister& fn, double value); 404 inline void Fcsel(const FPRegister& fd, 405 const FPRegister& fn, 406 const FPRegister& fm, 407 Condition cond); 408 inline void Fcvt(const FPRegister& fd, const FPRegister& fn); 409 inline void Fcvtas(const Register& rd, const FPRegister& fn); 410 inline void Fcvtau(const Register& rd, const FPRegister& fn); 411 inline void Fcvtms(const Register& rd, const FPRegister& fn); 412 inline void Fcvtmu(const Register& rd, const FPRegister& fn); 413 inline void Fcvtns(const Register& rd, const FPRegister& fn); 414 inline void Fcvtnu(const Register& rd, const FPRegister& fn); 415 inline void Fcvtzs(const Register& rd, const FPRegister& fn); 416 inline void Fcvtzu(const Register& rd, const FPRegister& fn); 417 inline void Fdiv(const FPRegister& fd, 418 const FPRegister& fn, 419 const FPRegister& fm); 420 inline void Fmadd(const FPRegister& fd, 421 const FPRegister& fn, 422 const FPRegister& fm, 423 const FPRegister& fa); 424 inline void Fmax(const FPRegister& fd, 425 const FPRegister& fn, 426 const FPRegister& fm); 427 inline void Fmaxnm(const FPRegister& fd, 428 const FPRegister& fn, 429 const FPRegister& fm); 430 inline void Fmin(const FPRegister& fd, 431 const FPRegister& fn, 432 const FPRegister& fm); 433 inline void Fminnm(const FPRegister& fd, 434 const FPRegister& fn, 435 const FPRegister& fm); 436 inline void Fmov(FPRegister fd, FPRegister fn); 437 inline void Fmov(FPRegister fd, Register rn); 438 // Provide explicit double and float interfaces for FP immediate moves, rather 439 // than relying on implicit C++ casts. This allows signalling NaNs to be 440 // preserved when the immediate matches the format of fd. Most systems convert 441 // signalling NaNs to quiet NaNs when converting between float and double. 442 inline void Fmov(FPRegister fd, double imm); 443 inline void Fmov(FPRegister fd, float imm); 444 // Provide a template to allow other types to be converted automatically. 445 template<typename T> 446 void Fmov(FPRegister fd, T imm) { 447 DCHECK(allow_macro_instructions_); 448 Fmov(fd, static_cast<double>(imm)); 449 } 450 inline void Fmov(Register rd, FPRegister fn); 451 inline void Fmsub(const FPRegister& fd, 452 const FPRegister& fn, 453 const FPRegister& fm, 454 const FPRegister& fa); 455 inline void Fmul(const FPRegister& fd, 456 const FPRegister& fn, 457 const FPRegister& fm); 458 inline void Fneg(const FPRegister& fd, const FPRegister& fn); 459 inline void Fnmadd(const FPRegister& fd, 460 const FPRegister& fn, 461 const FPRegister& fm, 462 const FPRegister& fa); 463 inline void Fnmsub(const FPRegister& fd, 464 const FPRegister& fn, 465 const FPRegister& fm, 466 const FPRegister& fa); 467 inline void Frinta(const FPRegister& fd, const FPRegister& fn); 468 inline void Frintm(const FPRegister& fd, const FPRegister& fn); 469 inline void Frintn(const FPRegister& fd, const FPRegister& fn); 470 inline void Frintp(const FPRegister& fd, const FPRegister& fn); 471 inline void Frintz(const FPRegister& fd, const FPRegister& fn); 472 inline void Fsqrt(const FPRegister& fd, const FPRegister& fn); 473 inline void Fsub(const FPRegister& fd, 474 const FPRegister& fn, 475 const FPRegister& fm); 476 inline void Hint(SystemHint code); 477 inline void Hlt(int code); 478 inline void Isb(); 479 inline void Ldnp(const CPURegister& rt, 480 const CPURegister& rt2, 481 const MemOperand& src); 482 // Load a literal from the inline constant pool. 483 inline void Ldr(const CPURegister& rt, const Immediate& imm); 484 // Helper function for double immediate. 485 inline void Ldr(const CPURegister& rt, double imm); 486 inline void Lsl(const Register& rd, const Register& rn, unsigned shift); 487 inline void Lsl(const Register& rd, const Register& rn, const Register& rm); 488 inline void Lsr(const Register& rd, const Register& rn, unsigned shift); 489 inline void Lsr(const Register& rd, const Register& rn, const Register& rm); 490 inline void Madd(const Register& rd, 491 const Register& rn, 492 const Register& rm, 493 const Register& ra); 494 inline void Mneg(const Register& rd, const Register& rn, const Register& rm); 495 inline void Mov(const Register& rd, const Register& rm); 496 inline void Movk(const Register& rd, uint64_t imm, int shift = -1); 497 inline void Mrs(const Register& rt, SystemRegister sysreg); 498 inline void Msr(SystemRegister sysreg, const Register& rt); 499 inline void Msub(const Register& rd, 500 const Register& rn, 501 const Register& rm, 502 const Register& ra); 503 inline void Mul(const Register& rd, const Register& rn, const Register& rm); 504 inline void Nop() { nop(); } 505 inline void Rbit(const Register& rd, const Register& rn); 506 inline void Ret(const Register& xn = lr); 507 inline void Rev(const Register& rd, const Register& rn); 508 inline void Rev16(const Register& rd, const Register& rn); 509 inline void Rev32(const Register& rd, const Register& rn); 510 inline void Ror(const Register& rd, const Register& rs, unsigned shift); 511 inline void Ror(const Register& rd, const Register& rn, const Register& rm); 512 inline void Sbfiz(const Register& rd, 513 const Register& rn, 514 unsigned lsb, 515 unsigned width); 516 inline void Sbfx(const Register& rd, 517 const Register& rn, 518 unsigned lsb, 519 unsigned width); 520 inline void Scvtf(const FPRegister& fd, 521 const Register& rn, 522 unsigned fbits = 0); 523 inline void Sdiv(const Register& rd, const Register& rn, const Register& rm); 524 inline void Smaddl(const Register& rd, 525 const Register& rn, 526 const Register& rm, 527 const Register& ra); 528 inline void Smsubl(const Register& rd, 529 const Register& rn, 530 const Register& rm, 531 const Register& ra); 532 inline void Smull(const Register& rd, 533 const Register& rn, 534 const Register& rm); 535 inline void Smulh(const Register& rd, 536 const Register& rn, 537 const Register& rm); 538 inline void Umull(const Register& rd, const Register& rn, const Register& rm); 539 inline void Stnp(const CPURegister& rt, 540 const CPURegister& rt2, 541 const MemOperand& dst); 542 inline void Sxtb(const Register& rd, const Register& rn); 543 inline void Sxth(const Register& rd, const Register& rn); 544 inline void Sxtw(const Register& rd, const Register& rn); 545 void Tbnz(const Register& rt, unsigned bit_pos, Label* label); 546 void Tbz(const Register& rt, unsigned bit_pos, Label* label); 547 inline void Ubfiz(const Register& rd, 548 const Register& rn, 549 unsigned lsb, 550 unsigned width); 551 inline void Ubfx(const Register& rd, 552 const Register& rn, 553 unsigned lsb, 554 unsigned width); 555 inline void Ucvtf(const FPRegister& fd, 556 const Register& rn, 557 unsigned fbits = 0); 558 inline void Udiv(const Register& rd, const Register& rn, const Register& rm); 559 inline void Umaddl(const Register& rd, 560 const Register& rn, 561 const Register& rm, 562 const Register& ra); 563 inline void Umsubl(const Register& rd, 564 const Register& rn, 565 const Register& rm, 566 const Register& ra); 567 inline void Uxtb(const Register& rd, const Register& rn); 568 inline void Uxth(const Register& rd, const Register& rn); 569 inline void Uxtw(const Register& rd, const Register& rn); 570 571 // Pseudo-instructions ------------------------------------------------------ 572 573 // Compute rd = abs(rm). 574 // This function clobbers the condition flags. On output the overflow flag is 575 // set iff the negation overflowed. 576 // 577 // If rm is the minimum representable value, the result is not representable. 578 // Handlers for each case can be specified using the relevant labels. 579 void Abs(const Register& rd, const Register& rm, 580 Label * is_not_representable = NULL, 581 Label * is_representable = NULL); 582 583 // Push or pop up to 4 registers of the same width to or from the stack, 584 // using the current stack pointer as set by SetStackPointer. 585 // 586 // If an argument register is 'NoReg', all further arguments are also assumed 587 // to be 'NoReg', and are thus not pushed or popped. 588 // 589 // Arguments are ordered such that "Push(a, b);" is functionally equivalent 590 // to "Push(a); Push(b);". 591 // 592 // It is valid to push the same register more than once, and there is no 593 // restriction on the order in which registers are specified. 594 // 595 // It is not valid to pop into the same register more than once in one 596 // operation, not even into the zero register. 597 // 598 // If the current stack pointer (as set by SetStackPointer) is csp, then it 599 // must be aligned to 16 bytes on entry and the total size of the specified 600 // registers must also be a multiple of 16 bytes. 601 // 602 // Even if the current stack pointer is not the system stack pointer (csp), 603 // Push (and derived methods) will still modify the system stack pointer in 604 // order to comply with ABI rules about accessing memory below the system 605 // stack pointer. 606 // 607 // Other than the registers passed into Pop, the stack pointer and (possibly) 608 // the system stack pointer, these methods do not modify any other registers. 609 void Push(const CPURegister& src0, const CPURegister& src1 = NoReg, 610 const CPURegister& src2 = NoReg, const CPURegister& src3 = NoReg); 611 void Push(const CPURegister& src0, const CPURegister& src1, 612 const CPURegister& src2, const CPURegister& src3, 613 const CPURegister& src4, const CPURegister& src5 = NoReg, 614 const CPURegister& src6 = NoReg, const CPURegister& src7 = NoReg); 615 void Pop(const CPURegister& dst0, const CPURegister& dst1 = NoReg, 616 const CPURegister& dst2 = NoReg, const CPURegister& dst3 = NoReg); 617 void Pop(const CPURegister& dst0, const CPURegister& dst1, 618 const CPURegister& dst2, const CPURegister& dst3, 619 const CPURegister& dst4, const CPURegister& dst5 = NoReg, 620 const CPURegister& dst6 = NoReg, const CPURegister& dst7 = NoReg); 621 void Push(const Register& src0, const FPRegister& src1); 622 623 // Alternative forms of Push and Pop, taking a RegList or CPURegList that 624 // specifies the registers that are to be pushed or popped. Higher-numbered 625 // registers are associated with higher memory addresses (as in the A32 push 626 // and pop instructions). 627 // 628 // (Push|Pop)SizeRegList allow you to specify the register size as a 629 // parameter. Only kXRegSizeInBits, kWRegSizeInBits, kDRegSizeInBits and 630 // kSRegSizeInBits are supported. 631 // 632 // Otherwise, (Push|Pop)(CPU|X|W|D|S)RegList is preferred. 633 void PushCPURegList(CPURegList registers); 634 void PopCPURegList(CPURegList registers); 635 636 inline void PushSizeRegList(RegList registers, unsigned reg_size, 637 CPURegister::RegisterType type = CPURegister::kRegister) { 638 PushCPURegList(CPURegList(type, reg_size, registers)); 639 } 640 inline void PopSizeRegList(RegList registers, unsigned reg_size, 641 CPURegister::RegisterType type = CPURegister::kRegister) { 642 PopCPURegList(CPURegList(type, reg_size, registers)); 643 } 644 inline void PushXRegList(RegList regs) { 645 PushSizeRegList(regs, kXRegSizeInBits); 646 } 647 inline void PopXRegList(RegList regs) { 648 PopSizeRegList(regs, kXRegSizeInBits); 649 } 650 inline void PushWRegList(RegList regs) { 651 PushSizeRegList(regs, kWRegSizeInBits); 652 } 653 inline void PopWRegList(RegList regs) { 654 PopSizeRegList(regs, kWRegSizeInBits); 655 } 656 inline void PushDRegList(RegList regs) { 657 PushSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister); 658 } 659 inline void PopDRegList(RegList regs) { 660 PopSizeRegList(regs, kDRegSizeInBits, CPURegister::kFPRegister); 661 } 662 inline void PushSRegList(RegList regs) { 663 PushSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister); 664 } 665 inline void PopSRegList(RegList regs) { 666 PopSizeRegList(regs, kSRegSizeInBits, CPURegister::kFPRegister); 667 } 668 669 // Push the specified register 'count' times. 670 void PushMultipleTimes(CPURegister src, Register count); 671 void PushMultipleTimes(CPURegister src, int count); 672 673 // This is a convenience method for pushing a single Handle<Object>. 674 inline void Push(Handle<Object> handle); 675 void Push(Smi* smi) { Push(Handle<Smi>(smi, isolate())); } 676 677 // Aliases of Push and Pop, required for V8 compatibility. 678 inline void push(Register src) { 679 Push(src); 680 } 681 inline void pop(Register dst) { 682 Pop(dst); 683 } 684 685 // Sometimes callers need to push or pop multiple registers in a way that is 686 // difficult to structure efficiently for fixed Push or Pop calls. This scope 687 // allows push requests to be queued up, then flushed at once. The 688 // MacroAssembler will try to generate the most efficient sequence required. 689 // 690 // Unlike the other Push and Pop macros, PushPopQueue can handle mixed sets of 691 // register sizes and types. 692 class PushPopQueue { 693 public: 694 explicit PushPopQueue(MacroAssembler* masm) : masm_(masm), size_(0) { } 695 696 ~PushPopQueue() { 697 DCHECK(queued_.empty()); 698 } 699 700 void Queue(const CPURegister& rt) { 701 size_ += rt.SizeInBytes(); 702 queued_.push_back(rt); 703 } 704 705 enum PreambleDirective { 706 WITH_PREAMBLE, 707 SKIP_PREAMBLE 708 }; 709 void PushQueued(PreambleDirective preamble_directive = WITH_PREAMBLE); 710 void PopQueued(); 711 712 private: 713 MacroAssembler* masm_; 714 int size_; 715 std::vector<CPURegister> queued_; 716 }; 717 718 // Poke 'src' onto the stack. The offset is in bytes. 719 // 720 // If the current stack pointer (according to StackPointer()) is csp, then 721 // csp must be aligned to 16 bytes. 722 void Poke(const CPURegister& src, const Operand& offset); 723 724 // Peek at a value on the stack, and put it in 'dst'. The offset is in bytes. 725 // 726 // If the current stack pointer (according to StackPointer()) is csp, then 727 // csp must be aligned to 16 bytes. 728 void Peek(const CPURegister& dst, const Operand& offset); 729 730 // Poke 'src1' and 'src2' onto the stack. The values written will be adjacent 731 // with 'src2' at a higher address than 'src1'. The offset is in bytes. 732 // 733 // If the current stack pointer (according to StackPointer()) is csp, then 734 // csp must be aligned to 16 bytes. 735 void PokePair(const CPURegister& src1, const CPURegister& src2, int offset); 736 737 // Peek at two values on the stack, and put them in 'dst1' and 'dst2'. The 738 // values peeked will be adjacent, with the value in 'dst2' being from a 739 // higher address than 'dst1'. The offset is in bytes. 740 // 741 // If the current stack pointer (according to StackPointer()) is csp, then 742 // csp must be aligned to 16 bytes. 743 void PeekPair(const CPURegister& dst1, const CPURegister& dst2, int offset); 744 745 // Emit code that loads |parameter_index|'th parameter from the stack to 746 // the register according to the CallInterfaceDescriptor definition. 747 // |sp_to_caller_sp_offset_in_words| specifies the number of words pushed 748 // below the caller's sp. 749 template <class Descriptor> 750 void LoadParameterFromStack( 751 Register reg, typename Descriptor::ParameterIndices parameter_index, 752 int sp_to_ra_offset_in_words = 0) { 753 DCHECK(Descriptor::kPassLastArgsOnStack); 754 UNIMPLEMENTED(); 755 } 756 757 // Claim or drop stack space without actually accessing memory. 758 // 759 // In debug mode, both of these will write invalid data into the claimed or 760 // dropped space. 761 // 762 // If the current stack pointer (according to StackPointer()) is csp, then it 763 // must be aligned to 16 bytes and the size claimed or dropped must be a 764 // multiple of 16 bytes. 765 // 766 // Note that unit_size must be specified in bytes. For variants which take a 767 // Register count, the unit size must be a power of two. 768 inline void Claim(int64_t count, uint64_t unit_size = kXRegSize); 769 inline void Claim(const Register& count, 770 uint64_t unit_size = kXRegSize); 771 inline void Drop(int64_t count, uint64_t unit_size = kXRegSize); 772 inline void Drop(const Register& count, 773 uint64_t unit_size = kXRegSize); 774 775 // Variants of Claim and Drop, where the 'count' parameter is a SMI held in a 776 // register. 777 inline void ClaimBySMI(const Register& count_smi, 778 uint64_t unit_size = kXRegSize); 779 inline void DropBySMI(const Register& count_smi, 780 uint64_t unit_size = kXRegSize); 781 782 // Compare a register with an operand, and branch to label depending on the 783 // condition. May corrupt the status flags. 784 inline void CompareAndBranch(const Register& lhs, 785 const Operand& rhs, 786 Condition cond, 787 Label* label); 788 789 // Test the bits of register defined by bit_pattern, and branch if ANY of 790 // those bits are set. May corrupt the status flags. 791 inline void TestAndBranchIfAnySet(const Register& reg, 792 const uint64_t bit_pattern, 793 Label* label); 794 795 // Test the bits of register defined by bit_pattern, and branch if ALL of 796 // those bits are clear (ie. not set.) May corrupt the status flags. 797 inline void TestAndBranchIfAllClear(const Register& reg, 798 const uint64_t bit_pattern, 799 Label* label); 800 801 // Insert one or more instructions into the instruction stream that encode 802 // some caller-defined data. The instructions used will be executable with no 803 // side effects. 804 inline void InlineData(uint64_t data); 805 806 // Insert an instrumentation enable marker into the instruction stream. 807 inline void EnableInstrumentation(); 808 809 // Insert an instrumentation disable marker into the instruction stream. 810 inline void DisableInstrumentation(); 811 812 // Insert an instrumentation event marker into the instruction stream. These 813 // will be picked up by the instrumentation system to annotate an instruction 814 // profile. The argument marker_name must be a printable two character string; 815 // it will be encoded in the event marker. 816 inline void AnnotateInstrumentation(const char* marker_name); 817 818 // If emit_debug_code() is true, emit a run-time check to ensure that 819 // StackPointer() does not point below the system stack pointer. 820 // 821 // Whilst it is architecturally legal for StackPointer() to point below csp, 822 // it can be evidence of a potential bug because the ABI forbids accesses 823 // below csp. 824 // 825 // If StackPointer() is the system stack pointer (csp), then csp will be 826 // dereferenced to cause the processor (or simulator) to abort if it is not 827 // properly aligned. 828 // 829 // If emit_debug_code() is false, this emits no code. 830 void AssertStackConsistency(); 831 832 // Emits a runtime assert that the CSP is aligned. 833 void AssertCspAligned(); 834 835 // Preserve the callee-saved registers (as defined by AAPCS64). 836 // 837 // Higher-numbered registers are pushed before lower-numbered registers, and 838 // thus get higher addresses. 839 // Floating-point registers are pushed before general-purpose registers, and 840 // thus get higher addresses. 841 // 842 // Note that registers are not checked for invalid values. Use this method 843 // only if you know that the GC won't try to examine the values on the stack. 844 // 845 // This method must not be called unless the current stack pointer (as set by 846 // SetStackPointer) is the system stack pointer (csp), and is aligned to 847 // ActivationFrameAlignment(). 848 void PushCalleeSavedRegisters(); 849 850 // Restore the callee-saved registers (as defined by AAPCS64). 851 // 852 // Higher-numbered registers are popped after lower-numbered registers, and 853 // thus come from higher addresses. 854 // Floating-point registers are popped after general-purpose registers, and 855 // thus come from higher addresses. 856 // 857 // This method must not be called unless the current stack pointer (as set by 858 // SetStackPointer) is the system stack pointer (csp), and is aligned to 859 // ActivationFrameAlignment(). 860 void PopCalleeSavedRegisters(); 861 862 // Set the current stack pointer, but don't generate any code. 863 inline void SetStackPointer(const Register& stack_pointer) { 864 DCHECK(!TmpList()->IncludesAliasOf(stack_pointer)); 865 sp_ = stack_pointer; 866 } 867 868 // Return the current stack pointer, as set by SetStackPointer. 869 inline const Register& StackPointer() const { 870 return sp_; 871 } 872 873 // Align csp for a frame, as per ActivationFrameAlignment, and make it the 874 // current stack pointer. 875 inline void AlignAndSetCSPForFrame() { 876 int sp_alignment = ActivationFrameAlignment(); 877 // AAPCS64 mandates at least 16-byte alignment. 878 DCHECK(sp_alignment >= 16); 879 DCHECK(base::bits::IsPowerOfTwo32(sp_alignment)); 880 Bic(csp, StackPointer(), sp_alignment - 1); 881 SetStackPointer(csp); 882 } 883 884 // Push the system stack pointer (csp) down to allow the same to be done to 885 // the current stack pointer (according to StackPointer()). This must be 886 // called _before_ accessing the memory. 887 // 888 // This is necessary when pushing or otherwise adding things to the stack, to 889 // satisfy the AAPCS64 constraint that the memory below the system stack 890 // pointer is not accessed. The amount pushed will be increased as necessary 891 // to ensure csp remains aligned to 16 bytes. 892 // 893 // This method asserts that StackPointer() is not csp, since the call does 894 // not make sense in that context. 895 inline void BumpSystemStackPointer(const Operand& space); 896 897 // Re-synchronizes the system stack pointer (csp) with the current stack 898 // pointer (according to StackPointer()). 899 // 900 // This method asserts that StackPointer() is not csp, since the call does 901 // not make sense in that context. 902 inline void SyncSystemStackPointer(); 903 904 // Helpers ------------------------------------------------------------------ 905 // Root register. 906 inline void InitializeRootRegister(); 907 908 void AssertFPCRState(Register fpcr = NoReg); 909 void CanonicalizeNaN(const FPRegister& dst, const FPRegister& src); 910 void CanonicalizeNaN(const FPRegister& reg) { 911 CanonicalizeNaN(reg, reg); 912 } 913 914 // Load an object from the root table. 915 void LoadRoot(CPURegister destination, 916 Heap::RootListIndex index); 917 // Store an object to the root table. 918 void StoreRoot(Register source, 919 Heap::RootListIndex index); 920 921 // Load both TrueValue and FalseValue roots. 922 void LoadTrueFalseRoots(Register true_root, Register false_root); 923 924 void LoadHeapObject(Register dst, Handle<HeapObject> object); 925 926 void LoadObject(Register result, Handle<Object> object) { 927 AllowDeferredHandleDereference heap_object_check; 928 if (object->IsHeapObject()) { 929 LoadHeapObject(result, Handle<HeapObject>::cast(object)); 930 } else { 931 DCHECK(object->IsSmi()); 932 Mov(result, Operand(object)); 933 } 934 } 935 936 static int SafepointRegisterStackIndex(int reg_code); 937 938 // This is required for compatibility with architecture independant code. 939 // Remove if not needed. 940 inline void Move(Register dst, Register src) { Mov(dst, src); } 941 inline void Move(Register dst, Handle<Object> x) { LoadObject(dst, x); } 942 inline void Move(Register dst, Smi* src) { Mov(dst, src); } 943 944 void LoadInstanceDescriptors(Register map, 945 Register descriptors); 946 void EnumLengthUntagged(Register dst, Register map); 947 void EnumLengthSmi(Register dst, Register map); 948 void NumberOfOwnDescriptors(Register dst, Register map); 949 void LoadAccessor(Register dst, Register holder, int accessor_index, 950 AccessorComponent accessor); 951 952 template<typename Field> 953 void DecodeField(Register dst, Register src) { 954 static const int shift = Field::kShift; 955 static const int setbits = CountSetBits(Field::kMask, 32); 956 Ubfx(dst, src, shift, setbits); 957 } 958 959 template<typename Field> 960 void DecodeField(Register reg) { 961 DecodeField<Field>(reg, reg); 962 } 963 964 // ---- SMI and Number Utilities ---- 965 966 inline void SmiTag(Register dst, Register src); 967 inline void SmiTag(Register smi); 968 inline void SmiUntag(Register dst, Register src); 969 inline void SmiUntag(Register smi); 970 inline void SmiUntagToDouble(FPRegister dst, 971 Register src, 972 UntagMode mode = kNotSpeculativeUntag); 973 inline void SmiUntagToFloat(FPRegister dst, 974 Register src, 975 UntagMode mode = kNotSpeculativeUntag); 976 977 // Tag and push in one step. 978 inline void SmiTagAndPush(Register src); 979 inline void SmiTagAndPush(Register src1, Register src2); 980 981 inline void JumpIfSmi(Register value, 982 Label* smi_label, 983 Label* not_smi_label = NULL); 984 inline void JumpIfNotSmi(Register value, Label* not_smi_label); 985 inline void JumpIfBothSmi(Register value1, 986 Register value2, 987 Label* both_smi_label, 988 Label* not_smi_label = NULL); 989 inline void JumpIfEitherSmi(Register value1, 990 Register value2, 991 Label* either_smi_label, 992 Label* not_smi_label = NULL); 993 inline void JumpIfEitherNotSmi(Register value1, 994 Register value2, 995 Label* not_smi_label); 996 inline void JumpIfBothNotSmi(Register value1, 997 Register value2, 998 Label* not_smi_label); 999 1000 // Abort execution if argument is a smi, enabled via --debug-code. 1001 void AssertNotSmi(Register object, BailoutReason reason = kOperandIsASmi); 1002 void AssertSmi(Register object, BailoutReason reason = kOperandIsNotASmi); 1003 1004 inline void ObjectTag(Register tagged_obj, Register obj); 1005 inline void ObjectUntag(Register untagged_obj, Register obj); 1006 1007 // Abort execution if argument is not a name, enabled via --debug-code. 1008 void AssertName(Register object); 1009 1010 // Abort execution if argument is not a JSFunction, enabled via --debug-code. 1011 void AssertFunction(Register object); 1012 1013 // Abort execution if argument is not a JSGeneratorObject, 1014 // enabled via --debug-code. 1015 void AssertGeneratorObject(Register object); 1016 1017 // Abort execution if argument is not a JSBoundFunction, 1018 // enabled via --debug-code. 1019 void AssertBoundFunction(Register object); 1020 1021 // Abort execution if argument is not a JSReceiver, enabled via --debug-code. 1022 void AssertReceiver(Register object); 1023 1024 // Abort execution if argument is not undefined or an AllocationSite, enabled 1025 // via --debug-code. 1026 void AssertUndefinedOrAllocationSite(Register object, Register scratch); 1027 1028 // Abort execution if argument is not a string, enabled via --debug-code. 1029 void AssertString(Register object); 1030 1031 // Abort execution if argument is not a positive or zero integer, enabled via 1032 // --debug-code. 1033 void AssertPositiveOrZero(Register value); 1034 1035 // Abort execution if argument is not a number (heap number or smi). 1036 void AssertNumber(Register value); 1037 void AssertNotNumber(Register value); 1038 1039 void JumpIfHeapNumber(Register object, Label* on_heap_number, 1040 SmiCheckType smi_check_type = DONT_DO_SMI_CHECK); 1041 void JumpIfNotHeapNumber(Register object, Label* on_not_heap_number, 1042 SmiCheckType smi_check_type = DONT_DO_SMI_CHECK); 1043 1044 // Sets the vs flag if the input is -0.0. 1045 void TestForMinusZero(DoubleRegister input); 1046 1047 // Jump to label if the input double register contains -0.0. 1048 void JumpIfMinusZero(DoubleRegister input, Label* on_negative_zero); 1049 1050 // Jump to label if the input integer register contains the double precision 1051 // floating point representation of -0.0. 1052 void JumpIfMinusZero(Register input, Label* on_negative_zero); 1053 1054 // Saturate a signed 32-bit integer in input to an unsigned 8-bit integer in 1055 // output. 1056 void ClampInt32ToUint8(Register in_out); 1057 void ClampInt32ToUint8(Register output, Register input); 1058 1059 // Saturate a double in input to an unsigned 8-bit integer in output. 1060 void ClampDoubleToUint8(Register output, 1061 DoubleRegister input, 1062 DoubleRegister dbl_scratch); 1063 1064 // Try to represent a double as a signed 32-bit int. 1065 // This succeeds if the result compares equal to the input, so inputs of -0.0 1066 // are represented as 0 and handled as a success. 1067 // 1068 // On output the Z flag is set if the operation was successful. 1069 void TryRepresentDoubleAsInt32(Register as_int, 1070 FPRegister value, 1071 FPRegister scratch_d, 1072 Label* on_successful_conversion = NULL, 1073 Label* on_failed_conversion = NULL) { 1074 DCHECK(as_int.Is32Bits()); 1075 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, 1076 on_failed_conversion); 1077 } 1078 1079 // Try to represent a double as a signed 64-bit int. 1080 // This succeeds if the result compares equal to the input, so inputs of -0.0 1081 // are represented as 0 and handled as a success. 1082 // 1083 // On output the Z flag is set if the operation was successful. 1084 void TryRepresentDoubleAsInt64(Register as_int, 1085 FPRegister value, 1086 FPRegister scratch_d, 1087 Label* on_successful_conversion = NULL, 1088 Label* on_failed_conversion = NULL) { 1089 DCHECK(as_int.Is64Bits()); 1090 TryRepresentDoubleAsInt(as_int, value, scratch_d, on_successful_conversion, 1091 on_failed_conversion); 1092 } 1093 1094 // ---- Object Utilities ---- 1095 1096 // Initialize fields with filler values. Fields starting at |current_address| 1097 // not including |end_address| are overwritten with the value in |filler|. At 1098 // the end the loop, |current_address| takes the value of |end_address|. 1099 void InitializeFieldsWithFiller(Register current_address, 1100 Register end_address, Register filler); 1101 1102 // ---- String Utilities ---- 1103 1104 // Checks if both instance types are sequential one-byte strings and jumps to 1105 // label if either is not. 1106 void JumpIfBothInstanceTypesAreNotSequentialOneByte( 1107 Register first_object_instance_type, Register second_object_instance_type, 1108 Register scratch1, Register scratch2, Label* failure); 1109 1110 void JumpIfNotUniqueNameInstanceType(Register type, Label* not_unique_name); 1111 1112 // ---- Calling / Jumping helpers ---- 1113 1114 // This is required for compatibility in architecture indepenedant code. 1115 inline void jmp(Label* L) { B(L); } 1116 1117 void CallStub(CodeStub* stub, TypeFeedbackId ast_id = TypeFeedbackId::None()); 1118 void TailCallStub(CodeStub* stub); 1119 1120 void CallRuntime(const Runtime::Function* f, 1121 int num_arguments, 1122 SaveFPRegsMode save_doubles = kDontSaveFPRegs); 1123 1124 // Convenience function: Same as above, but takes the fid instead. 1125 void CallRuntime(Runtime::FunctionId fid, int num_arguments, 1126 SaveFPRegsMode save_doubles = kDontSaveFPRegs) { 1127 CallRuntime(Runtime::FunctionForId(fid), num_arguments, save_doubles); 1128 } 1129 1130 // Convenience function: Same as above, but takes the fid instead. 1131 void CallRuntime(Runtime::FunctionId fid, 1132 SaveFPRegsMode save_doubles = kDontSaveFPRegs) { 1133 const Runtime::Function* function = Runtime::FunctionForId(fid); 1134 CallRuntime(function, function->nargs, save_doubles); 1135 } 1136 1137 void CallRuntimeSaveDoubles(Runtime::FunctionId fid) { 1138 const Runtime::Function* function = Runtime::FunctionForId(fid); 1139 CallRuntime(function, function->nargs, kSaveFPRegs); 1140 } 1141 1142 void TailCallRuntime(Runtime::FunctionId fid); 1143 1144 int ActivationFrameAlignment(); 1145 1146 // Calls a C function. 1147 // The called function is not allowed to trigger a 1148 // garbage collection, since that might move the code and invalidate the 1149 // return address (unless this is somehow accounted for by the called 1150 // function). 1151 void CallCFunction(ExternalReference function, 1152 int num_reg_arguments); 1153 void CallCFunction(ExternalReference function, 1154 int num_reg_arguments, 1155 int num_double_arguments); 1156 void CallCFunction(Register function, 1157 int num_reg_arguments, 1158 int num_double_arguments); 1159 1160 // Jump to a runtime routine. 1161 void JumpToExternalReference(const ExternalReference& builtin, 1162 bool builtin_exit_frame = false); 1163 1164 // Convenience function: call an external reference. 1165 void CallExternalReference(const ExternalReference& ext, 1166 int num_arguments); 1167 1168 1169 void Jump(Register target); 1170 void Jump(Address target, RelocInfo::Mode rmode, Condition cond = al); 1171 void Jump(Handle<Code> code, RelocInfo::Mode rmode, Condition cond = al); 1172 void Jump(intptr_t target, RelocInfo::Mode rmode, Condition cond = al); 1173 1174 void Call(Register target); 1175 void Call(Label* target); 1176 void Call(Address target, RelocInfo::Mode rmode); 1177 void Call(Handle<Code> code, 1178 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET, 1179 TypeFeedbackId ast_id = TypeFeedbackId::None()); 1180 1181 // For every Call variant, there is a matching CallSize function that returns 1182 // the size (in bytes) of the call sequence. 1183 static int CallSize(Register target); 1184 static int CallSize(Label* target); 1185 static int CallSize(Address target, RelocInfo::Mode rmode); 1186 static int CallSize(Handle<Code> code, 1187 RelocInfo::Mode rmode = RelocInfo::CODE_TARGET, 1188 TypeFeedbackId ast_id = TypeFeedbackId::None()); 1189 1190 // Removes current frame and its arguments from the stack preserving 1191 // the arguments and a return address pushed to the stack for the next call. 1192 // Both |callee_args_count| and |caller_args_count_reg| do not include 1193 // receiver. |callee_args_count| is not modified, |caller_args_count_reg| 1194 // is trashed. 1195 void PrepareForTailCall(const ParameterCount& callee_args_count, 1196 Register caller_args_count_reg, Register scratch0, 1197 Register scratch1); 1198 1199 // Registers used through the invocation chain are hard-coded. 1200 // We force passing the parameters to ensure the contracts are correctly 1201 // honoured by the caller. 1202 // 'function' must be x1. 1203 // 'actual' must use an immediate or x0. 1204 // 'expected' must use an immediate or x2. 1205 // 'call_kind' must be x5. 1206 void InvokePrologue(const ParameterCount& expected, 1207 const ParameterCount& actual, 1208 Label* done, 1209 InvokeFlag flag, 1210 bool* definitely_mismatches, 1211 const CallWrapper& call_wrapper); 1212 1213 // On function call, call into the debugger if necessary. 1214 void CheckDebugHook(Register fun, Register new_target, 1215 const ParameterCount& expected, 1216 const ParameterCount& actual); 1217 void InvokeFunctionCode(Register function, Register new_target, 1218 const ParameterCount& expected, 1219 const ParameterCount& actual, InvokeFlag flag, 1220 const CallWrapper& call_wrapper); 1221 // Invoke the JavaScript function in the given register. 1222 // Changes the current context to the context in the function before invoking. 1223 void InvokeFunction(Register function, 1224 Register new_target, 1225 const ParameterCount& actual, 1226 InvokeFlag flag, 1227 const CallWrapper& call_wrapper); 1228 void InvokeFunction(Register function, 1229 const ParameterCount& expected, 1230 const ParameterCount& actual, 1231 InvokeFlag flag, 1232 const CallWrapper& call_wrapper); 1233 void InvokeFunction(Handle<JSFunction> function, 1234 const ParameterCount& expected, 1235 const ParameterCount& actual, 1236 InvokeFlag flag, 1237 const CallWrapper& call_wrapper); 1238 1239 1240 // ---- Floating point helpers ---- 1241 1242 // Perform a conversion from a double to a signed int64. If the input fits in 1243 // range of the 64-bit result, execution branches to done. Otherwise, 1244 // execution falls through, and the sign of the result can be used to 1245 // determine if overflow was towards positive or negative infinity. 1246 // 1247 // On successful conversion, the least significant 32 bits of the result are 1248 // equivalent to the ECMA-262 operation "ToInt32". 1249 // 1250 // Only public for the test code in test-code-stubs-arm64.cc. 1251 void TryConvertDoubleToInt64(Register result, 1252 DoubleRegister input, 1253 Label* done); 1254 1255 // Performs a truncating conversion of a floating point number as used by 1256 // the JS bitwise operations. See ECMA-262 9.5: ToInt32. 1257 // Exits with 'result' holding the answer. 1258 void TruncateDoubleToI(Register result, DoubleRegister double_input); 1259 1260 // Performs a truncating conversion of a heap number as used by 1261 // the JS bitwise operations. See ECMA-262 9.5: ToInt32. 'result' and 'input' 1262 // must be different registers. Exits with 'result' holding the answer. 1263 void TruncateHeapNumberToI(Register result, Register object); 1264 1265 // Converts the smi or heap number in object to an int32 using the rules 1266 // for ToInt32 as described in ECMAScript 9.5.: the value is truncated 1267 // and brought into the range -2^31 .. +2^31 - 1. 'result' and 'input' must be 1268 // different registers. 1269 void TruncateNumberToI(Register object, 1270 Register result, 1271 Register heap_number_map, 1272 Label* not_int32); 1273 1274 // ---- Code generation helpers ---- 1275 1276 void set_generating_stub(bool value) { generating_stub_ = value; } 1277 bool generating_stub() const { return generating_stub_; } 1278 #if DEBUG 1279 void set_allow_macro_instructions(bool value) { 1280 allow_macro_instructions_ = value; 1281 } 1282 bool allow_macro_instructions() const { return allow_macro_instructions_; } 1283 #endif 1284 bool use_real_aborts() const { return use_real_aborts_; } 1285 void set_has_frame(bool value) { has_frame_ = value; } 1286 bool has_frame() const { return has_frame_; } 1287 bool AllowThisStubCall(CodeStub* stub); 1288 1289 class NoUseRealAbortsScope { 1290 public: 1291 explicit NoUseRealAbortsScope(MacroAssembler* masm) : 1292 saved_(masm->use_real_aborts_), masm_(masm) { 1293 masm_->use_real_aborts_ = false; 1294 } 1295 ~NoUseRealAbortsScope() { 1296 masm_->use_real_aborts_ = saved_; 1297 } 1298 private: 1299 bool saved_; 1300 MacroAssembler* masm_; 1301 }; 1302 1303 // Frame restart support 1304 void MaybeDropFrames(); 1305 1306 // Exception handling 1307 1308 // Push a new stack handler and link into stack handler chain. 1309 void PushStackHandler(); 1310 1311 // Unlink the stack handler on top of the stack from the stack handler chain. 1312 // Must preserve the result register. 1313 void PopStackHandler(); 1314 1315 1316 // --------------------------------------------------------------------------- 1317 // Allocation support 1318 1319 // Allocate an object in new space or old space. The object_size is 1320 // specified either in bytes or in words if the allocation flag SIZE_IN_WORDS 1321 // is passed. The allocated object is returned in result. 1322 // 1323 // If the new space is exhausted control continues at the gc_required label. 1324 // In this case, the result and scratch registers may still be clobbered. 1325 void Allocate(Register object_size, Register result, Register result_end, 1326 Register scratch, Label* gc_required, AllocationFlags flags); 1327 1328 void Allocate(int object_size, 1329 Register result, 1330 Register scratch1, 1331 Register scratch2, 1332 Label* gc_required, 1333 AllocationFlags flags); 1334 1335 // FastAllocate is right now only used for folded allocations. It just 1336 // increments the top pointer without checking against limit. This can only 1337 // be done if it was proved earlier that the allocation will succeed. 1338 void FastAllocate(Register object_size, Register result, Register result_end, 1339 Register scratch, AllocationFlags flags); 1340 1341 void FastAllocate(int object_size, Register result, Register scratch1, 1342 Register scratch2, AllocationFlags flags); 1343 1344 // Allocates a heap number or jumps to the gc_required label if the young 1345 // space is full and a scavenge is needed. 1346 // All registers are clobbered. 1347 // If no heap_number_map register is provided, the function will take care of 1348 // loading it. 1349 void AllocateHeapNumber(Register result, 1350 Label* gc_required, 1351 Register scratch1, 1352 Register scratch2, 1353 CPURegister value = NoFPReg, 1354 CPURegister heap_number_map = NoReg, 1355 MutableMode mode = IMMUTABLE); 1356 1357 // Allocate and initialize a JSValue wrapper with the specified {constructor} 1358 // and {value}. 1359 void AllocateJSValue(Register result, Register constructor, Register value, 1360 Register scratch1, Register scratch2, 1361 Label* gc_required); 1362 1363 // --------------------------------------------------------------------------- 1364 // Support functions. 1365 1366 // Machine code version of Map::GetConstructor(). 1367 // |temp| holds |result|'s map when done, and |temp2| its instance type. 1368 void GetMapConstructor(Register result, Register map, Register temp, 1369 Register temp2); 1370 1371 // Compare object type for heap object. heap_object contains a non-Smi 1372 // whose object type should be compared with the given type. This both 1373 // sets the flags and leaves the object type in the type_reg register. 1374 // It leaves the map in the map register (unless the type_reg and map register 1375 // are the same register). It leaves the heap object in the heap_object 1376 // register unless the heap_object register is the same register as one of the 1377 // other registers. 1378 void CompareObjectType(Register heap_object, 1379 Register map, 1380 Register type_reg, 1381 InstanceType type); 1382 1383 1384 // Compare object type for heap object, and branch if equal (or not.) 1385 // heap_object contains a non-Smi whose object type should be compared with 1386 // the given type. This both sets the flags and leaves the object type in 1387 // the type_reg register. It leaves the map in the map register (unless the 1388 // type_reg and map register are the same register). It leaves the heap 1389 // object in the heap_object register unless the heap_object register is the 1390 // same register as one of the other registers. 1391 void JumpIfObjectType(Register object, 1392 Register map, 1393 Register type_reg, 1394 InstanceType type, 1395 Label* if_cond_pass, 1396 Condition cond = eq); 1397 1398 void JumpIfNotObjectType(Register object, 1399 Register map, 1400 Register type_reg, 1401 InstanceType type, 1402 Label* if_not_object); 1403 1404 // Compare instance type in a map. map contains a valid map object whose 1405 // object type should be compared with the given type. This both 1406 // sets the flags and leaves the object type in the type_reg register. 1407 void CompareInstanceType(Register map, 1408 Register type_reg, 1409 InstanceType type); 1410 1411 // Compare an object's map with the specified map. Condition flags are set 1412 // with result of map compare. 1413 void CompareObjectMap(Register obj, Heap::RootListIndex index); 1414 1415 // Compare an object's map with the specified map. Condition flags are set 1416 // with result of map compare. 1417 void CompareObjectMap(Register obj, Register scratch, Handle<Map> map); 1418 1419 // As above, but the map of the object is already loaded into the register 1420 // which is preserved by the code generated. 1421 void CompareMap(Register obj_map, 1422 Handle<Map> map); 1423 1424 // Check if the map of an object is equal to a specified map and branch to 1425 // label if not. Skip the smi check if not required (object is known to be a 1426 // heap object). If mode is ALLOW_ELEMENT_TRANSITION_MAPS, then also match 1427 // against maps that are ElementsKind transition maps of the specified map. 1428 void CheckMap(Register obj, 1429 Register scratch, 1430 Handle<Map> map, 1431 Label* fail, 1432 SmiCheckType smi_check_type); 1433 1434 1435 void CheckMap(Register obj, 1436 Register scratch, 1437 Heap::RootListIndex index, 1438 Label* fail, 1439 SmiCheckType smi_check_type); 1440 1441 // As above, but the map of the object is already loaded into obj_map, and is 1442 // preserved. 1443 void CheckMap(Register obj_map, 1444 Handle<Map> map, 1445 Label* fail, 1446 SmiCheckType smi_check_type); 1447 1448 // Check if the map of an object is equal to a specified weak map and branch 1449 // to a specified target if equal. Skip the smi check if not required 1450 // (object is known to be a heap object) 1451 void DispatchWeakMap(Register obj, Register scratch1, Register scratch2, 1452 Handle<WeakCell> cell, Handle<Code> success, 1453 SmiCheckType smi_check_type); 1454 1455 // Compare the given value and the value of weak cell. 1456 void CmpWeakValue(Register value, Handle<WeakCell> cell, Register scratch); 1457 1458 void GetWeakValue(Register value, Handle<WeakCell> cell); 1459 1460 // Load the value of the weak cell in the value register. Branch to the given 1461 // miss label if the weak cell was cleared. 1462 void LoadWeakValue(Register value, Handle<WeakCell> cell, Label* miss); 1463 1464 // Test the bitfield of the heap object map with mask and set the condition 1465 // flags. The object register is preserved. 1466 void TestMapBitfield(Register object, uint64_t mask); 1467 1468 // Load the elements kind field from a map, and return it in the result 1469 // register. 1470 void LoadElementsKindFromMap(Register result, Register map); 1471 1472 // Load the value from the root list and push it onto the stack. 1473 void PushRoot(Heap::RootListIndex index); 1474 1475 // Compare the object in a register to a value from the root list. 1476 void CompareRoot(const Register& obj, Heap::RootListIndex index); 1477 1478 // Compare the object in a register to a value and jump if they are equal. 1479 void JumpIfRoot(const Register& obj, 1480 Heap::RootListIndex index, 1481 Label* if_equal); 1482 1483 // Compare the object in a register to a value and jump if they are not equal. 1484 void JumpIfNotRoot(const Register& obj, 1485 Heap::RootListIndex index, 1486 Label* if_not_equal); 1487 1488 // Load and check the instance type of an object for being a unique name. 1489 // Loads the type into the second argument register. 1490 // The object and type arguments can be the same register; in that case it 1491 // will be overwritten with the type. 1492 // Fall-through if the object was a string and jump on fail otherwise. 1493 inline void IsObjectNameType(Register object, Register type, Label* fail); 1494 1495 // Load and check the instance type of an object for being a string. 1496 // Loads the type into the second argument register. 1497 // The object and type arguments can be the same register; in that case it 1498 // will be overwritten with the type. 1499 // Jumps to not_string or string appropriate. If the appropriate label is 1500 // NULL, fall through. 1501 inline void IsObjectJSStringType(Register object, Register type, 1502 Label* not_string, Label* string = NULL); 1503 1504 // Compare the contents of a register with an operand, and branch to true, 1505 // false or fall through, depending on condition. 1506 void CompareAndSplit(const Register& lhs, 1507 const Operand& rhs, 1508 Condition cond, 1509 Label* if_true, 1510 Label* if_false, 1511 Label* fall_through); 1512 1513 // Test the bits of register defined by bit_pattern, and branch to 1514 // if_any_set, if_all_clear or fall_through accordingly. 1515 void TestAndSplit(const Register& reg, 1516 uint64_t bit_pattern, 1517 Label* if_all_clear, 1518 Label* if_any_set, 1519 Label* fall_through); 1520 1521 // --------------------------------------------------------------------------- 1522 // Inline caching support. 1523 1524 void EmitSeqStringSetCharCheck(Register string, 1525 Register index, 1526 SeqStringSetCharCheckIndexType index_type, 1527 Register scratch, 1528 uint32_t encoding_mask); 1529 1530 // Hash the interger value in 'key' register. 1531 // It uses the same algorithm as ComputeIntegerHash in utils.h. 1532 void GetNumberHash(Register key, Register scratch); 1533 1534 // --------------------------------------------------------------------------- 1535 // Frames. 1536 1537 // Load the type feedback vector from a JavaScript frame. 1538 void EmitLoadFeedbackVector(Register vector); 1539 1540 // Activation support. 1541 void EnterFrame(StackFrame::Type type); 1542 void EnterFrame(StackFrame::Type type, bool load_constant_pool_pointer_reg); 1543 void LeaveFrame(StackFrame::Type type); 1544 1545 void EnterBuiltinFrame(Register context, Register target, Register argc); 1546 void LeaveBuiltinFrame(Register context, Register target, Register argc); 1547 1548 // Returns map with validated enum cache in object register. 1549 void CheckEnumCache(Register object, Register scratch0, Register scratch1, 1550 Register scratch2, Register scratch3, Register scratch4, 1551 Label* call_runtime); 1552 1553 // AllocationMemento support. Arrays may have an associated 1554 // AllocationMemento object that can be checked for in order to pretransition 1555 // to another type. 1556 // On entry, receiver should point to the array object. 1557 // If allocation info is present, the Z flag is set (so that the eq 1558 // condition will pass). 1559 void TestJSArrayForAllocationMemento(Register receiver, 1560 Register scratch1, 1561 Register scratch2, 1562 Label* no_memento_found); 1563 1564 // The stack pointer has to switch between csp and jssp when setting up and 1565 // destroying the exit frame. Hence preserving/restoring the registers is 1566 // slightly more complicated than simple push/pop operations. 1567 void ExitFramePreserveFPRegs(); 1568 void ExitFrameRestoreFPRegs(); 1569 1570 // Generates function and stub prologue code. 1571 void StubPrologue(StackFrame::Type type, int frame_slots); 1572 void Prologue(bool code_pre_aging); 1573 1574 // Enter exit frame. Exit frames are used when calling C code from generated 1575 // (JavaScript) code. 1576 // 1577 // The stack pointer must be jssp on entry, and will be set to csp by this 1578 // function. The frame pointer is also configured, but the only other 1579 // registers modified by this function are the provided scratch register, and 1580 // jssp. 1581 // 1582 // The 'extra_space' argument can be used to allocate some space in the exit 1583 // frame that will be ignored by the GC. This space will be reserved in the 1584 // bottom of the frame immediately above the return address slot. 1585 // 1586 // Set up a stack frame and registers as follows: 1587 // fp[8]: CallerPC (lr) 1588 // fp -> fp[0]: CallerFP (old fp) 1589 // fp[-8]: SPOffset (new csp) 1590 // fp[-16]: CodeObject() 1591 // fp[-16 - fp-size]: Saved doubles, if saved_doubles is true. 1592 // csp[8]: Memory reserved for the caller if extra_space != 0. 1593 // Alignment padding, if necessary. 1594 // csp -> csp[0]: Space reserved for the return address. 1595 // 1596 // This function also stores the new frame information in the top frame, so 1597 // that the new frame becomes the current frame. 1598 void EnterExitFrame(bool save_doubles, const Register& scratch, 1599 int extra_space = 0, 1600 StackFrame::Type frame_type = StackFrame::EXIT); 1601 1602 // Leave the current exit frame, after a C function has returned to generated 1603 // (JavaScript) code. 1604 // 1605 // This effectively unwinds the operation of EnterExitFrame: 1606 // * Preserved doubles are restored (if restore_doubles is true). 1607 // * The frame information is removed from the top frame. 1608 // * The exit frame is dropped. 1609 // * The stack pointer is reset to jssp. 1610 // 1611 // The stack pointer must be csp on entry. 1612 void LeaveExitFrame(bool save_doubles, 1613 const Register& scratch, 1614 bool restore_context); 1615 1616 void LoadContext(Register dst, int context_chain_length); 1617 1618 // Load the global object from the current context. 1619 void LoadGlobalObject(Register dst) { 1620 LoadNativeContextSlot(Context::EXTENSION_INDEX, dst); 1621 } 1622 1623 // Load the global proxy from the current context. 1624 void LoadGlobalProxy(Register dst) { 1625 LoadNativeContextSlot(Context::GLOBAL_PROXY_INDEX, dst); 1626 } 1627 1628 // Emit code for a truncating division by a constant. The dividend register is 1629 // unchanged. Dividend and result must be different. 1630 void TruncatingDiv(Register result, Register dividend, int32_t divisor); 1631 1632 // --------------------------------------------------------------------------- 1633 // StatsCounter support 1634 1635 void SetCounter(StatsCounter* counter, int value, Register scratch1, 1636 Register scratch2); 1637 void IncrementCounter(StatsCounter* counter, int value, Register scratch1, 1638 Register scratch2); 1639 void DecrementCounter(StatsCounter* counter, int value, Register scratch1, 1640 Register scratch2); 1641 1642 // --------------------------------------------------------------------------- 1643 // Garbage collector support (GC). 1644 1645 enum RememberedSetFinalAction { 1646 kReturnAtEnd, 1647 kFallThroughAtEnd 1648 }; 1649 1650 // Record in the remembered set the fact that we have a pointer to new space 1651 // at the address pointed to by the addr register. Only works if addr is not 1652 // in new space. 1653 void RememberedSetHelper(Register object, // Used for debug code. 1654 Register addr, 1655 Register scratch1, 1656 SaveFPRegsMode save_fp, 1657 RememberedSetFinalAction and_then); 1658 1659 // Push and pop the registers that can hold pointers, as defined by the 1660 // RegList constant kSafepointSavedRegisters. 1661 void PushSafepointRegisters(); 1662 void PopSafepointRegisters(); 1663 1664 void PushSafepointRegistersAndDoubles(); 1665 void PopSafepointRegistersAndDoubles(); 1666 1667 // Store value in register src in the safepoint stack slot for register dst. 1668 void StoreToSafepointRegisterSlot(Register src, Register dst) { 1669 Poke(src, SafepointRegisterStackIndex(dst.code()) * kPointerSize); 1670 } 1671 1672 // Load the value of the src register from its safepoint stack slot 1673 // into register dst. 1674 void LoadFromSafepointRegisterSlot(Register dst, Register src) { 1675 Peek(src, SafepointRegisterStackIndex(dst.code()) * kPointerSize); 1676 } 1677 1678 void CheckPageFlag(const Register& object, const Register& scratch, int mask, 1679 Condition cc, Label* condition_met); 1680 1681 void CheckPageFlagSet(const Register& object, 1682 const Register& scratch, 1683 int mask, 1684 Label* if_any_set); 1685 1686 void CheckPageFlagClear(const Register& object, 1687 const Register& scratch, 1688 int mask, 1689 Label* if_all_clear); 1690 1691 // Check if object is in new space and jump accordingly. 1692 // Register 'object' is preserved. 1693 void JumpIfNotInNewSpace(Register object, 1694 Label* branch) { 1695 InNewSpace(object, ne, branch); 1696 } 1697 1698 void JumpIfInNewSpace(Register object, 1699 Label* branch) { 1700 InNewSpace(object, eq, branch); 1701 } 1702 1703 // Notify the garbage collector that we wrote a pointer into an object. 1704 // |object| is the object being stored into, |value| is the object being 1705 // stored. value and scratch registers are clobbered by the operation. 1706 // The offset is the offset from the start of the object, not the offset from 1707 // the tagged HeapObject pointer. For use with FieldMemOperand(reg, off). 1708 void RecordWriteField( 1709 Register object, 1710 int offset, 1711 Register value, 1712 Register scratch, 1713 LinkRegisterStatus lr_status, 1714 SaveFPRegsMode save_fp, 1715 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET, 1716 SmiCheck smi_check = INLINE_SMI_CHECK, 1717 PointersToHereCheck pointers_to_here_check_for_value = 1718 kPointersToHereMaybeInteresting); 1719 1720 // As above, but the offset has the tag presubtracted. For use with 1721 // MemOperand(reg, off). 1722 inline void RecordWriteContextSlot( 1723 Register context, 1724 int offset, 1725 Register value, 1726 Register scratch, 1727 LinkRegisterStatus lr_status, 1728 SaveFPRegsMode save_fp, 1729 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET, 1730 SmiCheck smi_check = INLINE_SMI_CHECK, 1731 PointersToHereCheck pointers_to_here_check_for_value = 1732 kPointersToHereMaybeInteresting) { 1733 RecordWriteField(context, 1734 offset + kHeapObjectTag, 1735 value, 1736 scratch, 1737 lr_status, 1738 save_fp, 1739 remembered_set_action, 1740 smi_check, 1741 pointers_to_here_check_for_value); 1742 } 1743 1744 // Notify the garbage collector that we wrote a code entry into a 1745 // JSFunction. Only scratch is clobbered by the operation. 1746 void RecordWriteCodeEntryField(Register js_function, Register code_entry, 1747 Register scratch); 1748 1749 void RecordWriteForMap( 1750 Register object, 1751 Register map, 1752 Register dst, 1753 LinkRegisterStatus lr_status, 1754 SaveFPRegsMode save_fp); 1755 1756 // For a given |object| notify the garbage collector that the slot |address| 1757 // has been written. |value| is the object being stored. The value and 1758 // address registers are clobbered by the operation. 1759 void RecordWrite( 1760 Register object, 1761 Register address, 1762 Register value, 1763 LinkRegisterStatus lr_status, 1764 SaveFPRegsMode save_fp, 1765 RememberedSetAction remembered_set_action = EMIT_REMEMBERED_SET, 1766 SmiCheck smi_check = INLINE_SMI_CHECK, 1767 PointersToHereCheck pointers_to_here_check_for_value = 1768 kPointersToHereMaybeInteresting); 1769 1770 // Checks the color of an object. If the object is white we jump to the 1771 // incremental marker. 1772 void JumpIfWhite(Register value, Register scratch1, Register scratch2, 1773 Register scratch3, Register scratch4, Label* value_is_white); 1774 1775 // Helper for finding the mark bits for an address. 1776 // Note that the behaviour slightly differs from other architectures. 1777 // On exit: 1778 // - addr_reg is unchanged. 1779 // - The bitmap register points at the word with the mark bits. 1780 // - The shift register contains the index of the first color bit for this 1781 // object in the bitmap. 1782 inline void GetMarkBits(Register addr_reg, 1783 Register bitmap_reg, 1784 Register shift_reg); 1785 1786 // Check if an object has a given incremental marking color. 1787 void HasColor(Register object, 1788 Register scratch0, 1789 Register scratch1, 1790 Label* has_color, 1791 int first_bit, 1792 int second_bit); 1793 1794 void JumpIfBlack(Register object, 1795 Register scratch0, 1796 Register scratch1, 1797 Label* on_black); 1798 1799 1800 // --------------------------------------------------------------------------- 1801 // Debugging. 1802 1803 // Calls Abort(msg) if the condition cond is not satisfied. 1804 // Use --debug_code to enable. 1805 void Assert(Condition cond, BailoutReason reason); 1806 void AssertRegisterIsClear(Register reg, BailoutReason reason); 1807 void AssertRegisterIsRoot( 1808 Register reg, 1809 Heap::RootListIndex index, 1810 BailoutReason reason = kRegisterDidNotMatchExpectedRoot); 1811 void AssertFastElements(Register elements); 1812 1813 // Abort if the specified register contains the invalid color bit pattern. 1814 // The pattern must be in bits [1:0] of 'reg' register. 1815 // 1816 // If emit_debug_code() is false, this emits no code. 1817 void AssertHasValidColor(const Register& reg); 1818 1819 // Abort if 'object' register doesn't point to a string object. 1820 // 1821 // If emit_debug_code() is false, this emits no code. 1822 void AssertIsString(const Register& object); 1823 1824 // Like Assert(), but always enabled. 1825 void Check(Condition cond, BailoutReason reason); 1826 void CheckRegisterIsClear(Register reg, BailoutReason reason); 1827 1828 // Print a message to stderr and abort execution. 1829 void Abort(BailoutReason reason); 1830 1831 void LoadNativeContextSlot(int index, Register dst); 1832 1833 // Load the initial map from the global function. The registers function and 1834 // map can be the same, function is then overwritten. 1835 void LoadGlobalFunctionInitialMap(Register function, 1836 Register map, 1837 Register scratch); 1838 1839 CPURegList* TmpList() { return &tmp_list_; } 1840 CPURegList* FPTmpList() { return &fptmp_list_; } 1841 1842 static CPURegList DefaultTmpList(); 1843 static CPURegList DefaultFPTmpList(); 1844 1845 // Like printf, but print at run-time from generated code. 1846 // 1847 // The caller must ensure that arguments for floating-point placeholders 1848 // (such as %e, %f or %g) are FPRegisters, and that arguments for integer 1849 // placeholders are Registers. 1850 // 1851 // At the moment it is only possible to print the value of csp if it is the 1852 // current stack pointer. Otherwise, the MacroAssembler will automatically 1853 // update csp on every push (using BumpSystemStackPointer), so determining its 1854 // value is difficult. 1855 // 1856 // Format placeholders that refer to more than one argument, or to a specific 1857 // argument, are not supported. This includes formats like "%1$d" or "%.*d". 1858 // 1859 // This function automatically preserves caller-saved registers so that 1860 // calling code can use Printf at any point without having to worry about 1861 // corruption. The preservation mechanism generates a lot of code. If this is 1862 // a problem, preserve the important registers manually and then call 1863 // PrintfNoPreserve. Callee-saved registers are not used by Printf, and are 1864 // implicitly preserved. 1865 void Printf(const char * format, 1866 CPURegister arg0 = NoCPUReg, 1867 CPURegister arg1 = NoCPUReg, 1868 CPURegister arg2 = NoCPUReg, 1869 CPURegister arg3 = NoCPUReg); 1870 1871 // Like Printf, but don't preserve any caller-saved registers, not even 'lr'. 1872 // 1873 // The return code from the system printf call will be returned in x0. 1874 void PrintfNoPreserve(const char * format, 1875 const CPURegister& arg0 = NoCPUReg, 1876 const CPURegister& arg1 = NoCPUReg, 1877 const CPURegister& arg2 = NoCPUReg, 1878 const CPURegister& arg3 = NoCPUReg); 1879 1880 // Code ageing support functions. 1881 1882 // Code ageing on ARM64 works similarly to on ARM. When V8 wants to mark a 1883 // function as old, it replaces some of the function prologue (generated by 1884 // FullCodeGenerator::Generate) with a call to a special stub (ultimately 1885 // generated by GenerateMakeCodeYoungAgainCommon). The stub restores the 1886 // function prologue to its initial young state (indicating that it has been 1887 // recently run) and continues. A young function is therefore one which has a 1888 // normal frame setup sequence, and an old function has a code age sequence 1889 // which calls a code ageing stub. 1890 1891 // Set up a basic stack frame for young code (or code exempt from ageing) with 1892 // type FUNCTION. It may be patched later for code ageing support. This is 1893 // done by to Code::PatchPlatformCodeAge and EmitCodeAgeSequence. 1894 // 1895 // This function takes an Assembler so it can be called from either a 1896 // MacroAssembler or a PatchingAssembler context. 1897 static void EmitFrameSetupForCodeAgePatching(Assembler* assm); 1898 1899 // Call EmitFrameSetupForCodeAgePatching from a MacroAssembler context. 1900 void EmitFrameSetupForCodeAgePatching(); 1901 1902 // Emit a code age sequence that calls the relevant code age stub. The code 1903 // generated by this sequence is expected to replace the code generated by 1904 // EmitFrameSetupForCodeAgePatching, and represents an old function. 1905 // 1906 // If stub is NULL, this function generates the code age sequence but omits 1907 // the stub address that is normally embedded in the instruction stream. This 1908 // can be used by debug code to verify code age sequences. 1909 static void EmitCodeAgeSequence(Assembler* assm, Code* stub); 1910 1911 // Call EmitCodeAgeSequence from a MacroAssembler context. 1912 void EmitCodeAgeSequence(Code* stub); 1913 1914 // Return true if the sequence is a young sequence geneated by 1915 // EmitFrameSetupForCodeAgePatching. Otherwise, this method asserts that the 1916 // sequence is a code age sequence (emitted by EmitCodeAgeSequence). 1917 static bool IsYoungSequence(Isolate* isolate, byte* sequence); 1918 1919 // Perform necessary maintenance operations before a push or after a pop. 1920 // 1921 // Note that size is specified in bytes. 1922 void PushPreamble(Operand total_size); 1923 void PopPostamble(Operand total_size); 1924 1925 void PushPreamble(int count, int size) { PushPreamble(count * size); } 1926 void PopPostamble(int count, int size) { PopPostamble(count * size); } 1927 1928 private: 1929 // The actual Push and Pop implementations. These don't generate any code 1930 // other than that required for the push or pop. This allows 1931 // (Push|Pop)CPURegList to bundle together run-time assertions for a large 1932 // block of registers. 1933 // 1934 // Note that size is per register, and is specified in bytes. 1935 void PushHelper(int count, int size, 1936 const CPURegister& src0, const CPURegister& src1, 1937 const CPURegister& src2, const CPURegister& src3); 1938 void PopHelper(int count, int size, 1939 const CPURegister& dst0, const CPURegister& dst1, 1940 const CPURegister& dst2, const CPURegister& dst3); 1941 1942 // Call Printf. On a native build, a simple call will be generated, but if the 1943 // simulator is being used then a suitable pseudo-instruction is used. The 1944 // arguments and stack (csp) must be prepared by the caller as for a normal 1945 // AAPCS64 call to 'printf'. 1946 // 1947 // The 'args' argument should point to an array of variable arguments in their 1948 // proper PCS registers (and in calling order). The argument registers can 1949 // have mixed types. The format string (x0) should not be included. 1950 void CallPrintf(int arg_count = 0, const CPURegister * args = NULL); 1951 1952 // Helper for implementing JumpIfNotInNewSpace and JumpIfInNewSpace. 1953 void InNewSpace(Register object, 1954 Condition cond, // eq for new space, ne otherwise. 1955 Label* branch); 1956 1957 // Try to represent a double as an int so that integer fast-paths may be 1958 // used. Not every valid integer value is guaranteed to be caught. 1959 // It supports both 32-bit and 64-bit integers depending whether 'as_int' 1960 // is a W or X register. 1961 // 1962 // This does not distinguish between +0 and -0, so if this distinction is 1963 // important it must be checked separately. 1964 // 1965 // On output the Z flag is set if the operation was successful. 1966 void TryRepresentDoubleAsInt(Register as_int, 1967 FPRegister value, 1968 FPRegister scratch_d, 1969 Label* on_successful_conversion = NULL, 1970 Label* on_failed_conversion = NULL); 1971 1972 bool generating_stub_; 1973 #if DEBUG 1974 // Tell whether any of the macro instruction can be used. When false the 1975 // MacroAssembler will assert if a method which can emit a variable number 1976 // of instructions is called. 1977 bool allow_macro_instructions_; 1978 #endif 1979 bool has_frame_; 1980 1981 // The Abort method should call a V8 runtime function, but the CallRuntime 1982 // mechanism depends on CEntryStub. If use_real_aborts is false, Abort will 1983 // use a simpler abort mechanism that doesn't depend on CEntryStub. 1984 // 1985 // The purpose of this is to allow Aborts to be compiled whilst CEntryStub is 1986 // being generated. 1987 bool use_real_aborts_; 1988 1989 // This handle will be patched with the code object on installation. 1990 Handle<Object> code_object_; 1991 1992 // The register to use as a stack pointer for stack operations. 1993 Register sp_; 1994 1995 // Scratch registers available for use by the MacroAssembler. 1996 CPURegList tmp_list_; 1997 CPURegList fptmp_list_; 1998 1999 public: 2000 // Far branches resolving. 2001 // 2002 // The various classes of branch instructions with immediate offsets have 2003 // different ranges. While the Assembler will fail to assemble a branch 2004 // exceeding its range, the MacroAssembler offers a mechanism to resolve 2005 // branches to too distant targets, either by tweaking the generated code to 2006 // use branch instructions with wider ranges or generating veneers. 2007 // 2008 // Currently branches to distant targets are resolved using unconditional 2009 // branch isntructions with a range of +-128MB. If that becomes too little 2010 // (!), the mechanism can be extended to generate special veneers for really 2011 // far targets. 2012 2013 // Helps resolve branching to labels potentially out of range. 2014 // If the label is not bound, it registers the information necessary to later 2015 // be able to emit a veneer for this branch if necessary. 2016 // If the label is bound, it returns true if the label (or the previous link 2017 // in the label chain) is out of range. In that case the caller is responsible 2018 // for generating appropriate code. 2019 // Otherwise it returns false. 2020 // This function also checks wether veneers need to be emitted. 2021 bool NeedExtraInstructionsOrRegisterBranch(Label *label, 2022 ImmBranchType branch_type); 2023 }; 2024 2025 2026 // Use this scope when you need a one-to-one mapping bewteen methods and 2027 // instructions. This scope prevents the MacroAssembler from being called and 2028 // literal pools from being emitted. It also asserts the number of instructions 2029 // emitted is what you specified when creating the scope. 2030 class InstructionAccurateScope BASE_EMBEDDED { 2031 public: 2032 explicit InstructionAccurateScope(MacroAssembler* masm, size_t count = 0) 2033 : masm_(masm) 2034 #ifdef DEBUG 2035 , 2036 size_(count * kInstructionSize) 2037 #endif 2038 { 2039 // Before blocking the const pool, see if it needs to be emitted. 2040 masm_->CheckConstPool(false, true); 2041 masm_->CheckVeneerPool(false, true); 2042 2043 masm_->StartBlockPools(); 2044 #ifdef DEBUG 2045 if (count != 0) { 2046 masm_->bind(&start_); 2047 } 2048 previous_allow_macro_instructions_ = masm_->allow_macro_instructions(); 2049 masm_->set_allow_macro_instructions(false); 2050 #endif 2051 } 2052 2053 ~InstructionAccurateScope() { 2054 masm_->EndBlockPools(); 2055 #ifdef DEBUG 2056 if (start_.is_bound()) { 2057 DCHECK(masm_->SizeOfCodeGeneratedSince(&start_) == size_); 2058 } 2059 masm_->set_allow_macro_instructions(previous_allow_macro_instructions_); 2060 #endif 2061 } 2062 2063 private: 2064 MacroAssembler* masm_; 2065 #ifdef DEBUG 2066 size_t size_; 2067 Label start_; 2068 bool previous_allow_macro_instructions_; 2069 #endif 2070 }; 2071 2072 2073 // This scope utility allows scratch registers to be managed safely. The 2074 // MacroAssembler's TmpList() (and FPTmpList()) is used as a pool of scratch 2075 // registers. These registers can be allocated on demand, and will be returned 2076 // at the end of the scope. 2077 // 2078 // When the scope ends, the MacroAssembler's lists will be restored to their 2079 // original state, even if the lists were modified by some other means. 2080 class UseScratchRegisterScope { 2081 public: 2082 explicit UseScratchRegisterScope(MacroAssembler* masm) 2083 : available_(masm->TmpList()), 2084 availablefp_(masm->FPTmpList()), 2085 old_available_(available_->list()), 2086 old_availablefp_(availablefp_->list()) { 2087 DCHECK(available_->type() == CPURegister::kRegister); 2088 DCHECK(availablefp_->type() == CPURegister::kFPRegister); 2089 } 2090 2091 ~UseScratchRegisterScope(); 2092 2093 // Take a register from the appropriate temps list. It will be returned 2094 // automatically when the scope ends. 2095 Register AcquireW() { return AcquireNextAvailable(available_).W(); } 2096 Register AcquireX() { return AcquireNextAvailable(available_).X(); } 2097 FPRegister AcquireS() { return AcquireNextAvailable(availablefp_).S(); } 2098 FPRegister AcquireD() { return AcquireNextAvailable(availablefp_).D(); } 2099 2100 Register UnsafeAcquire(const Register& reg) { 2101 return Register(UnsafeAcquire(available_, reg)); 2102 } 2103 2104 Register AcquireSameSizeAs(const Register& reg); 2105 FPRegister AcquireSameSizeAs(const FPRegister& reg); 2106 2107 private: 2108 static CPURegister AcquireNextAvailable(CPURegList* available); 2109 static CPURegister UnsafeAcquire(CPURegList* available, 2110 const CPURegister& reg); 2111 2112 // Available scratch registers. 2113 CPURegList* available_; // kRegister 2114 CPURegList* availablefp_; // kFPRegister 2115 2116 // The state of the available lists at the start of this scope. 2117 RegList old_available_; // kRegister 2118 RegList old_availablefp_; // kFPRegister 2119 }; 2120 2121 2122 inline MemOperand ContextMemOperand(Register context, int index = 0) { 2123 return MemOperand(context, Context::SlotOffset(index)); 2124 } 2125 2126 inline MemOperand NativeContextMemOperand() { 2127 return ContextMemOperand(cp, Context::NATIVE_CONTEXT_INDEX); 2128 } 2129 2130 2131 // Encode and decode information about patchable inline SMI checks. 2132 class InlineSmiCheckInfo { 2133 public: 2134 explicit InlineSmiCheckInfo(Address info); 2135 2136 bool HasSmiCheck() const { 2137 return smi_check_ != NULL; 2138 } 2139 2140 const Register& SmiRegister() const { 2141 return reg_; 2142 } 2143 2144 Instruction* SmiCheck() const { 2145 return smi_check_; 2146 } 2147 2148 int SmiCheckDelta() const { return smi_check_delta_; } 2149 2150 // Use MacroAssembler::InlineData to emit information about patchable inline 2151 // SMI checks. The caller may specify 'reg' as NoReg and an unbound 'site' to 2152 // indicate that there is no inline SMI check. Note that 'reg' cannot be csp. 2153 // 2154 // The generated patch information can be read using the InlineSMICheckInfo 2155 // class. 2156 static void Emit(MacroAssembler* masm, const Register& reg, 2157 const Label* smi_check); 2158 2159 // Emit information to indicate that there is no inline SMI check. 2160 static void EmitNotInlined(MacroAssembler* masm) { 2161 Label unbound; 2162 Emit(masm, NoReg, &unbound); 2163 } 2164 2165 private: 2166 Register reg_; 2167 int smi_check_delta_; 2168 Instruction* smi_check_; 2169 2170 // Fields in the data encoded by InlineData. 2171 2172 // A width of 5 (Rd_width) for the SMI register preclues the use of csp, 2173 // since kSPRegInternalCode is 63. However, csp should never hold a SMI or be 2174 // used in a patchable check. The Emit() method checks this. 2175 // 2176 // Note that the total size of the fields is restricted by the underlying 2177 // storage size handled by the BitField class, which is a uint32_t. 2178 class RegisterBits : public BitField<unsigned, 0, 5> {}; 2179 class DeltaBits : public BitField<uint32_t, 5, 32-5> {}; 2180 }; 2181 2182 } // namespace internal 2183 } // namespace v8 2184 2185 #define ACCESS_MASM(masm) masm-> 2186 2187 #endif // V8_ARM64_MACRO_ASSEMBLER_ARM64_H_ 2188
