| /external/vixl/test/aarch32/ |
| test-disasm-a32.cc | 514 "adcs r0, #2\n");
525 "adcs r0, ip\n");
532 "adcs r0, ip\n");
558 "adcs r0, r2\n");
562 "adcs r0, r1\n");
566 "adcs r0, ip, r0\n");
577 "adcs r0, ip, r0, lsr #2\n");
585 "adcs r0, ip, r0, ror #4\n");
599 "adcs r0, ip, r0\n");
609 "adcs r0, ip\n")
[all...] |
| test-assembler-aarch32.cc | 296 __ Adcs(r3, r2, r1);
311 __ Adcs(r3, r2, Operand(r1, ASR, 31));
326 __ Adcs(r3, r2, Operand(r1, LSR, 31));
341 __ Adcs(r3, r2, Operand(r1, LSL, 4));
356 __ Adcs(r3, r2, Operand(r1, ROR, 8));
371 __ Adcs(r3, r2, Operand(r1, RRX));
386 __ Adcs(r3, r2, Operand(r1, RRX));
[all...] |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 117 M(Adcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 117 M(Adcs) \
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 242 void MacroAssembler::Adcs(const Register& rd,
[all...] |
| macro-assembler-arm64.h | 234 inline void Adcs(const Register& rd,
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | [all...] |
| macro-assembler-aarch64.h | 686 void Adcs(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
