| /external/v8/src/arm64/ |
| assembler-arm64.cc | 264 bool AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2,
[all...] |
| macro-assembler-arm64.cc | 846 DCHECK(AreSameSizeAndType(rd, rm));
870 DCHECK(AreSameSizeAndType(src0, src1, src2, src3));
884 DCHECK(AreSameSizeAndType(src0, src1, src2, src3, src4, src5, src6, src7));
900 DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3));
918 DCHECK(AreSameSizeAndType(dst0, dst1, dst2, dst3, dst4, dst5, dst6, dst7));
[all...] |
| assembler-arm64-inl.h | 897 DCHECK(AreSameSizeAndType(rt, rt2));
921 DCHECK(AreSameSizeAndType(rt, rt2));
[all...] |
| assembler-arm64.h | 364 // AreSameSizeAndType returns true if all of the specified registers have the
368 bool AreSameSizeAndType(const CPURegister& reg1,
393 DCHECK(AreSameSizeAndType(reg1, reg2, reg3, reg4));
[all...] |
| /external/vixl/src/aarch64/ |
| operands-aarch64.h | 484 // AreSameSizeAndType returns true if all of the specified registers have the
488 bool AreSameSizeAndType(const CPURegister& reg1,
527 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4));
|
| macro-assembler-aarch64.cc | [all...] |
| assembler-aarch64.cc | 803 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
819 VIXL_ASSERT(AreSameSizeAndType(rd, rn, rm));
974 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
1016 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
[all...] |
