| /device/linaro/bootloader/edk2/OvmfPkg/Include/IndustryStandard/ |
| I440FxPiix4.h | 36 #define PIIX4_PMBA_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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| Q35MchIch9.h | 79 #define ICH9_PMBASE_MASK (BIT15 | BIT14 | BIT13 | BIT12 | BIT11 | \
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| Virtio095Net.h | 54 #define VIRTIO_NET_F_HOST_ECN BIT13 // host can receive TSO with ECN
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/ |
| PchRegsUsb.h | 69 #define B_PCH_EHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13) // Data Scale
92 #define B_PCH_XHCI_PWR_CNTL_STS_DATASCL (BIT14 | BIT13)
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| PchRegsSpi.h | 48 #define B_PCH_SPI_HSFS_FDOPSS BIT13 // Flash Descriptor Override Pin-Strap Status
77 #define B_PCH_SPI_OPTYPE6_MASK (BIT13 | BIT12) // Opcode Type 6 Mask
97 #define B_PCH_SPI_FDOC_FDSS_MASK (BIT14 | BIT13 | BIT12) // Flash Descriptor Section Select
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| PchRegsSata.h | 82 #define B_PCH_SATA_PCISTS_RMA BIT13 // Received Master-Abort Status
170 #define B_PCH_SATA_MAP_SPD (BIT14 | BIT13 | BIT12 | BIT11 | BIT10 | BIT9 | BIT8) // SATA Port Disable
172 #define B_PCH_SATA_PORT5_DISABLED BIT13
188 #define B_PCH_SATA_PCS_PORT5_DET BIT13 // Port 5 Present
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| PchRegsPcu.h | 90 #define B_PCH_LPC_DEV_STS_RMA BIT13 // Received Master Abort
197 #define B_PCH_LPC_FWH_BIOS_DEC_EE8 BIT13 // E8-EF Enable
353 #define B_PCH_ILB_DXXIR_IDR_MASK (BIT14 | BIT13 | BIT12) // INTD Mask
356 #define V_PCH_ILB_DXXIR_IDR_PIRQC BIT13 // INTD Mapping to IRQ C
357 #define V_PCH_ILB_DXXIR_IDR_PIRQD (BIT13 | BIT12) // INTD Mapping to IRQ D
360 #define V_PCH_ILB_DXXIR_IDR_PIRQG (BIT14 | BIT13) // INTD Mapping to IRQ G
361 #define V_PCH_ILB_DXXIR_IDR_PIRQH (BIT14 | BIT13 | BIT12) // INTD Mapping to IRQ H
466 #define B_PCH_ACPI_PM1_STS_USB_CLKLESS BIT13 // USB Clockless Status
485 #define B_PCH_ACPI_PM1_EN_USB_CLKLESS BIT13 // USB Clockless Enable Bit
500 #define B_PCH_ACPI_PM1_CNT_SLP_EN BIT13 // Sleep enable
[all...] |
| /device/linaro/bootloader/OpenPlatformPkg/Drivers/Net/Lan91xDxe/ |
| Lan91xDxeHw.h | 83 #define TCR_EPH_LOOP BIT13
110 #define RCR_ABORT_ENB BIT13
126 #define RPCR_SPEED BIT13
178 #define PTR_READ BIT13
208 #define RX_BAD_CRC BIT13
218 #define PCW_ODD BIT13
250 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
263 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
276 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Lan9118Dxe/ |
| Lan9118DxeHw.h | 143 #define RXSTATUS_BCF BIT13 // Frame has Broadcast Address
169 #define IRQCFG_INT_DEAS_STS BIT13 // State of deassertion interval
182 #define INSTS_TXE BIT13 // Transmitter Error
216 #define MPTCTRL_PM_MODE_MASK (BIT12 | BIT13) // Set the power mode
224 #define PHYCR_SPEED_SEL BIT13 // Link Speed Selection
237 #define PHYSTS_100BASETX_HDPLX BIT13 // 100Mbps Half-Duplex ability
248 #define PHYANA_REMOTE_FAULT BIT13 // Remote fault detected
279 #define MACCR_HPFILT BIT13 // Hash/Perfect Filtering Mode bit
380 #define TX_CMD_A_FIRST_SEGMENT BIT13
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| /device/linaro/bootloader/edk2/Omap35xxPkg/Include/Omap3530/ |
| Omap3530Dma.h | 51 #define DMA4_CSDP_DST_PACKED BIT13
97 #define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)
98 #define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)
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| Omap3530Prcm.h | 112 #define CM_FCLKEN_PER_EN_GPIO2_ENABLE BIT13
137 #define CM_ICLKEN_PER_EN_GPIO2_ENABLE BIT13
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| /system/bt/embdrv/sbc/decoder/include/ |
| oi_bt_spec.h | 193 #define OI_BT_DEV_CLASS_LIMITED_DISCO_BIT BIT13
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| /device/linaro/bootloader/edk2/CorebootPayloadPkg/Library/ResetSystemLib/ |
| ResetSystemLib.c | 42 IoOr16 (PmCtrlReg, BIT13);
141 IoOr16 (PmCtrlReg, BIT13);
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| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/ |
| general_definitions.h | 30 #undef BIT13
66 #define BIT13 0x00002000U
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| meminit.c | 565 isbM32m(DDRPHY, (B0ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
566 isbM32m(DDRPHY, (B1ONDURCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT13|BIT12|BIT11|BIT10|BIT9|BIT8))); // On Duration: ODT, DIFFAMP
572 isbM32m(DDRPHY, (B0OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
573 isbM32m(DDRPHY, (B1OVRCTL + (bl_grp_i * DDRIODQ_BL_OFFSET) + (channel_i * DDRIODQ_CH_OFFSET)), tempD, ((BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10))); // Override: DIFFAMP, ODT
602 isbM32m(DDRPHY, (CMDPMDLYREG4 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFFFU<<16)|(0xFFFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: SFR (regulator), MPLL
603 isbM32m(DDRPHY, (CMDPMDLYREG3 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFU<<28)|(0xFFF<<16)|(0xF<<12)|(0x616<<0)), ((BIT31|BIT30|BIT29|BIT28)|(BIT27|BIT26|BIT25|BIT24|BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Delays: ASSERT_IOBUFACT_to_ALLON0_for_PM_MSG_3, VREG (MDLL) Turn On, ALLON0_to_DEASSERT_IOBUFACT_for_PM_MSG_gt0, MDLL Turn On
604 isbM32m(DDRPHY, (CMDPMDLYREG2 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // MPLL Divider Reset Delays
605 isbM32m(DDRPHY, (CMDPMDLYREG1 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn Off Delays: VREG, Staggered MDLL, MDLL, PI
606 isbM32m(DDRPHY, (CMDPMDLYREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0xFFU<<24)|(0xFF<<16)|(0xFF<<8)|(0xFF<<0)), ((BIT31|BIT30|BIT29|BIT28|BIT27|BIT26|BIT25|BIT24)|(BIT23|BIT22|BIT21|BIT20|BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12|BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0))); // Turn On Delays: MPLL, Staggered MDLL, PI, IOBUFACT
611 isbM32m(DDRPHY, (CCCFGREG0 + (channel_i * DDRIOCCC_CH_OFFSET)), ((0x0<<16)|(0x0<<12)|(0x0<<8)|(0xF<<4)|BIT0), ((BIT19|BIT18|BIT17|BIT16)|(BIT15|BIT14|BIT13|BIT12)|(BIT11|BIT10|BIT9|BIT8)|(BIT7|BIT6|BIT5|BIT4)|BIT0)); // Buffer Enable: CS,CKE,ODT,CLK
[all...] |
| /device/linaro/bootloader/edk2/BeagleBoardPkg/Library/BeagleBoardLib/ |
| BeagleBoard.c | 48 MmioWrite32(GPIO6_BASE + GPIO_OE, (OldPinDir | BIT11 | BIT12 | BIT13));
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| /device/linaro/bootloader/edk2/OvmfPkg/Library/ResetSystemLib/ |
| ResetSystemLib.c | 50 IoOr16 (AcpiPmBaseAddress + 4, BIT13);
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| /device/linaro/bootloader/edk2/MdePkg/Library/BasePrintLib/ |
| PrintLibInternal.h | 36 #define COUNT_ONLY_NO_PRINT BIT13
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/ |
| CommonIncludes.h | 103 #define BIT13 0x00002000
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| /device/linaro/bootloader/edk2/EmbeddedPkg/Drivers/Isp1761UsbDxe/ |
| Isp1761UsbDxe.h | 54 #define ISP1761_DC_INTERRUPT_EP1TX BIT13
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| /device/linaro/bootloader/edk2/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/ |
| PchRegs.h | 59 #define BIT13 0x2000
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| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| BoardFeatures.h | 60 #define B_BOARD_FEATURES_TPM BIT13
154 #define B_BOARD_FEATURES_USB_HUB BIT13
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/Include/ |
| QuarkNcSocId.h | 173 #define SCRUB_CFG_ACTIVE (BIT13)
463 #define B_QNC_PM1BLK_PM1C_SLPEN (BIT13)
482 #define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE
489 #define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE
659 #define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask
[all...] |
| /device/linaro/bootloader/edk2/ArmPlatformPkg/Drivers/PL180MciDxe/ |
| PL180Mci.h | 96 #define MCI_STATUS_CMD_RXACTIVE BIT13
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| /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/Common/ |
| BaseTypes.h | 234 #define BIT13 0x00002000
|
