| /external/llvm/lib/Target/PowerPC/ |
| PPCEarlyReturn.cpp | 47 // branch-to-blr sequences.
63 // The block must be essentially empty except for the blr.
65 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) ||
84 // branch with a blr.
156 // We now might be able to merge this blr-only block into its
161 // Move the blr into the preceding block.
|
| PPCInstrInfo.cpp | [all...] |
| PPCFrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 411 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg));
513 /// blr x1
554 MCInst Blr;
555 Blr.setOpcode(AArch64::BLR);
556 Blr.addOperand(MCOperand::createReg(AArch64::X1));
557 EmitToStreamer(*OutStreamer, Blr);
|
| AArch64FastISel.cpp | [all...] |
| /external/v8/src/arm64/ |
| instructions-arm64.h | 335 return Mask(UnconditionalBranchToRegisterMask) == BLR;
|
| disasm-arm64.cc | 543 case BLR: mnemonic = "blr"; break;
[all...] |
| assembler-arm64-inl.h | 562 Emit(BLR | Rn(xzr));
591 // blr ip0
608 // blr temp
612 // blr temp
614 // The return address is immediately after the blr instruction in both cases,
[all...] |
| constants-arm64.h | 612 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
[all...] |
| assembler-arm64.cc | 363 // blr xzr
376 // blr xzr
406 // blr xzr
410 // instruction following the offending blr.
921 // 4: blr xzr
959 Emit(BLR | Rn(xzr));
983 void Assembler::blr(const Register& xn) { function in class:v8::internal::Assembler
985 // The pattern 'blr xzr' is used as a guard to detect when execution falls
988 Emit(BLR | Rn(xn));
[all...] |
| simulator-arm64.cc | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| RegisterCoalescer.cpp | 430 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
431 if (BLR == IntB.end()) return false;
432 VNInfo *BValNo = BLR->valno;
489 if (ValLR+1 != BLR) return false;
510 SlotIndex FillerStart = ValLR->end, FillerEnd = BLR->start;
518 // [ValLR.end, BLR.begin) of either value number, then we merge the
727 // If ALR and BLR overlaps and end of BLR extends beyond end of ALR, e.g.
[all...] |
| /external/selinux/mcstrans/share/examples/nato/setrans.d/ |
| eyes-only.conf | 97 ~c228=BLR # Belarus
|
| rel.conf | 103 ~c200,~c228=BLR # Belarus
|
| /external/pcre/dist2/src/sljit/ |
| sljitNativeARM_64.c | 74 #define BLR 0xd63f0000
[all...] |
| sljitNativePPC_common.c | 149 #define BLR (HI(19) | LO(16) | (0x14 << 21))
695 FAIL_IF(push_inst(compiler, BLR));
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 513 assert((RetOpcode == PPC::BLR ||
658 if (GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| plan9x.go | 87 case BLR:
|
| tables.go | 41 BLR
510 BLR: "BLR",
1096 // BLR <Xn>
1097 {0xfffffc1f, 0xd63f0000, BLR, instArgs{arg_Xn}, nil},
[all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm64/arm64asm/ |
| plan9x.go | 87 case BLR:
|
| tables.go | 41 BLR
510 BLR: "BLR",
1096 // BLR <Xn>
1097 {0xfffffc1f, 0xd63f0000, BLR, instArgs{arg_Xn}, nil},
[all...] |
| /toolchain/binutils/binutils-2.27/bfd/ |
| elf64-ppc.c | 235 #define BLR 0x4e800020 /* blr */
[all...] |
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 652 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000,
[all...] |
| disasm-aarch64.cc | 613 case BLR:
614 mnemonic = "blr";
[all...] |
| simulator-aarch64.cc | 1024 case BLR:
[all...] |
