| /toolchain/binutils/binutils-2.27/include/opcode/ |
| cris.h | 155 #define CC_NE 0x2
|
| /toolchain/binutils/binutils-2.27/opcodes/ |
| cris-opc.c | 435 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
436 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
1023 0x0530+CC_NE*0x1000,
1024 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
[all...] |
| fr30-desc.h | 96 CC_RA, CC_NO, CC_EQ, CC_NE
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| nv50_ir.h | 281 CC_NE = 5,
282 CC_P = CC_NE,
[all...] |
| nv50_ir_lowering_nv50.cpp | [all...] |
| nv50_ir_lowering_nvc0.cpp | [all...] |
| nv50_ir.cpp | 475 case CC_NE: return reg.data.f32 != fval;
|
| nv50_ir_from_tgsi.cpp | 700 return CC_NE;
[all...] |
| nv50_ir_emit_gm107.cpp | 370 case CC_NE : data = 0x05; break;
393 case CC_NE: data = 0x05; break;
[all...] |
| nv50_ir_emit_gk110.cpp | 275 case CC_NE: n = 0x05; break;
[all...] |
| nv50_ir_emit_nv50.cpp | 220 case CC_NE: enc = 0x5; break;
[all...] |
| nv50_ir_emit_nvc0.cpp | 249 case CC_NE: val = 0x5; break;
[all...] |
| nv50_ir_peephole.cpp | [all...] |
