| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| mrs-msr-arm-v6.d | 11 0+0c <[^>]*> e328f101 msr CPSR_f, #1073741824 ; 0x40000000
12 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
14 0+18 <[^>]*> e128f004 msr CPSR_f, r4
15 0+1c <[^>]*> e128f005 msr CPSR_f, r5
|
| mrs-msr-arm-v7-a.d | 12 0+10 <[^>]*> e328f202 msr CPSR_f, #536870912 ; 0x20000000
14 0+18 <[^>]*> e128f004 msr CPSR_f, r4
15 0+1c <[^>]*> e128f005 msr CPSR_f, r5
|
| arm6.d | 11 0+0c <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
17 0+24 <[^>]+> 1328f20f ? msrne CPSR_f, #-268435456 ; 0xf0000000
|
| arch4t.s | 22 msr CPSR_f, #2
26 msr CPSR_f, r6
|
| mrs-msr-thumb-v6t2.d | 14 0+10 <[^>]*> f385 8800 msr CPSR_f, r5
|
| arch4t-eabi.d | 26 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
30 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6
|
| arch4t.d | 24 0+38 <[^>]+> e328f002 ? msr CPSR_f, #2
28 0+48 <[^>]+> e128f006 ? msr CPSR_f, r6
|
| archv6m.d | 7 0[0-9a-f]+ <[^>]+> f386 8800 msr (APSR|CPSR_f), r6
|
| mrs-msr-thumb-v7-m.d | 14 0+10 <[^>]*> f384 8800 msr CPSR_f, r4
|
| msr-imm.d | 8 00000000 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
10 00000008 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
14 00000018 <[^>]*> e328f113 msr CPSR_f, #-1073741820 ; 0xc0000004
|
| msr-reg.d | 9 00000000 <[^>]*> e128f009 msr CPSR_f, r9
11 00000008 <[^>]*> e128f009 msr CPSR_f, r9
15 00000018 <[^>]*> e128f009 msr CPSR_f, r9
|
| arch7.d | 49 # V7M APSR has the same encoding as V7A CPSR_f
64 0+0d8 <[^>]*> f380 8800 msr (CPSR_f|APSR_nzcvq), r0
|
| msr-reg-thumb.d | 11 00000000 <[^>]*> f389 8800 msr CPSR_f, r9
13 00000008 <[^>]*> f389 8800 msr CPSR_f, r9
17 00000018 <[^>]*> f389 8800 msr CPSR_f, r9
|
| msr-imm.s | 17 msr CPSR_f,#0xc0000004
|
| msr-reg.s | 16 msr CPSR_f,r9
|
| msr-imm-bad.l | 8 [^:]*:17: Error: Thumb encoding does not support an immediate here -- `msr CPSR_f,#0xc0000004'
|
| msr-reg-bad.l | 7 [^:]*:16: Error: selected processor does not support requested special purpose register -- `msr CPSR_f,r9'
|
| thumb32.s | 479 msr CPSR_f, r0
|
| thumb32.d | 660 0[0-9a-f]+ <[^>]+> f380 8800 msr CPSR_f, r0
[all...] |
| /external/compiler-rt/lib/builtins/arm/ |
| aeabi_cdcmp.S | 38 msr CPSR_f, #APSR_C
72 msr CPSR_f, ip
|
| aeabi_cfcmp.S | 38 msr CPSR_f, #APSR_C
72 msr CPSR_f, ip
|
| /external/v8/src/arm/ |
| constants-arm.h | 276 CPSR_f = CPSR | 1 << 19,
|
| simulator-arm.cc | [all...] |
| /external/vixl/src/aarch32/ |
| instructions-aarch32.h | 850 CPSR_f = APSR_nzcvq,
[all...] |
