| /external/vixl/test/aarch64/ |
| test-api-aarch64.cc | 131 // Test the same as before, but using CPURegister types. This shouldn't make
133 VIXL_CHECK(static_cast<CPURegister>(x0).IsValid());
134 VIXL_CHECK(static_cast<CPURegister>(w0).IsValid());
135 VIXL_CHECK(static_cast<CPURegister>(x30).IsValid());
136 VIXL_CHECK(static_cast<CPURegister>(w30).IsValid());
137 VIXL_CHECK(static_cast<CPURegister>(xzr).IsValid());
138 VIXL_CHECK(static_cast<CPURegister>(wzr).IsValid());
140 VIXL_CHECK(static_cast<CPURegister>(sp).IsValid());
141 VIXL_CHECK(static_cast<CPURegister>(wsp).IsValid());
143 VIXL_CHECK(static_cast<CPURegister>(d0).IsValid())
[all...] |
| /external/vixl/examples/aarch64/ |
| custom-disassembler.h | 49 const CPURegister& reg) VIXL_OVERRIDE;
|
| custom-disassembler.cc | 36 const CPURegister& reg) {
|
| /external/vixl/src/aarch64/ |
| operands-aarch64.h | 41 // Some CPURegister methods can return Register or VRegister types, so we need
46 class CPURegister {
58 CPURegister() : code_(0), size_(0), type_(kNoRegister) {
63 CPURegister(unsigned code, unsigned size, RegisterType type)
168 bool Aliases(const CPURegister& other) const {
173 bool Is(const CPURegister& other) const {
219 bool IsSameType(const CPURegister& other) const {
223 bool IsSameSizeAndType(const CPURegister& other) const {
237 class Register : public CPURegister {
239 Register() : CPURegister() {}
[all...] |
| operands-aarch64.cc | 33 CPURegister CPURegList::PopLowestIndex() {
40 return CPURegister(index, size_, type_);
44 CPURegister CPURegList::PopHighestIndex() {
53 return CPURegister(index, size_, type_);
58 if ((type_ == CPURegister::kRegister) || (type_ == CPURegister::kVRegister)) {
60 // Try to create a CPURegister for each element in the list.
63 is_valid &= CPURegister(i, size_, type_).IsValid();
67 } else if (type_ == CPURegister::kNoRegister) {
77 if (GetType() == CPURegister::kRegister)
[all...] |
| macro-assembler-aarch64.cc | [all...] |
| macro-assembler-aarch64.h | 53 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \
54 V(Str, CPURegister&, rt, StoreOpFor(rt)) \
59 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
60 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
61 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
771 void LoadStoreMacro(const CPURegister& rt,
780 void LoadStorePairMacro(const CPURegister& rt,
781 const CPURegister& rt2,
813 void Push(const CPURegister& src0,
814 const CPURegister& src1 = NoReg
[all...] |
| assembler-aarch64.h | [all...] |
| disasm-aarch64.h | 63 const CPURegister& reg);
|
| assembler-aarch64.cc | 946 void Assembler::ldp(const CPURegister& rt,
947 const CPURegister& rt2,
953 void Assembler::stp(const CPURegister& rt,
954 const CPURegister& rt2,
968 void Assembler::LoadStorePair(const CPURegister& rt,
969 const CPURegister& rt2,
997 void Assembler::ldnp(const CPURegister& rt,
998 const CPURegister& rt2,
1004 void Assembler::stnp(const CPURegister& rt,
1005 const CPURegister& rt2
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.h | 62 V(Ldr, CPURegister&, rt, LoadOpFor(rt)) \
63 V(Str, CPURegister&, rt, StoreOpFor(rt)) \
67 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
68 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
69 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
301 void LoadStoreMacro(const CPURegister& rt,
310 void LoadStorePairMacro(const CPURegister& rt, const CPURegister& rt2,
479 inline void Ldnp(const CPURegister& rt,
480 const CPURegister& rt2
[all...] |
| assembler-arm64.h | 69 // Some CPURegister methods can return Register and FPRegister types, so we
75 struct CPURegister {
93 static CPURegister Create(int code, int size, RegisterType type) {
94 CPURegister r = {code, size, type};
110 bool Is(const CPURegister& other) const;
111 bool Aliases(const CPURegister& other) const;
124 bool IsSameSizeAndType(const CPURegister& other) const;
127 bool is(const CPURegister& other) const { return Is(other); }
136 struct Register : public CPURegister {
138 return Register(CPURegister::Create(code, size, CPURegister::kRegister))
[all...] |
| assembler-arm64-inl.h | 30 inline int CPURegister::code() const {
36 inline CPURegister::RegisterType CPURegister::type() const {
42 inline RegList CPURegister::Bit() const {
48 inline int CPURegister::SizeInBits() const {
54 inline int CPURegister::SizeInBytes() const {
61 inline bool CPURegister::Is32Bits() const {
67 inline bool CPURegister::Is64Bits() const {
73 inline bool CPURegister::IsValid() const {
84 inline bool CPURegister::IsValidRegister() const
[all...] |
| macro-assembler-arm64.cc | 562 void MacroAssembler::LoadStoreMacro(const CPURegister& rt,
593 void MacroAssembler::LoadStorePairMacro(const CPURegister& rt,
594 const CPURegister& rt2,
868 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1,
869 const CPURegister& src2, const CPURegister& src3) {
880 void MacroAssembler::Push(const CPURegister& src0, const CPURegister& src1,
881 const CPURegister& src2, const CPURegister& src3
[all...] |
| deoptimizer-arm64.cc | 99 CPURegister::kFPRegister, kDRegSizeInBits,
104 CPURegList saved_registers(CPURegister::kRegister, kXRegSizeInBits, 0, 27);
162 CPURegister current_reg = copy_to_input.PopLowestIndex();
173 CPURegister reg = copy_fp_to_input.PopLowestIndex();
248 const CPURegister reg = saved_fp_registers.PopLowestIndex();
282 CPURegister current_reg = saved_registers.PopLowestIndex();
|
| assembler-arm64.cc | 65 CPURegister CPURegList::PopLowestIndex() {
73 return CPURegister::Create(index, size_, type_);
77 CPURegister CPURegList::PopHighestIndex() {
86 return CPURegister::Create(index, size_, type_);
91 if (type() == CPURegister::kRegister) {
93 } else if (type() == CPURegister::kFPRegister) {
96 DCHECK(type() == CPURegister::kNoRegister);
104 return CPURegList(CPURegister::kRegister, size, 19, 29);
109 return CPURegList(CPURegister::kFPRegister, size, 8, 15);
115 CPURegList list = CPURegList(CPURegister::kRegister, size, 0, 18)
[all...] |
| /art/compiler/utils/arm64/ |
| assembler_arm64.cc | 74 static inline dwarf::Reg DWARFReg(CPURegister reg) {
90 const CPURegister& dst0 = registers.PopLowestIndex();
96 const CPURegister& dst0 = registers.PopLowestIndex();
97 const CPURegister& dst1 = registers.PopLowestIndex();
104 const CPURegister& dst0 = registers.PopLowestIndex();
116 const CPURegister& dst0 = registers.PopLowestIndex();
122 const CPURegister& dst0 = registers.PopLowestIndex();
123 const CPURegister& dst1 = registers.PopLowestIndex();
130 const CPURegister& dst0 = registers.PopLowestIndex();
|
| /external/v8/src/crankshaft/arm64/ |
| delayed-masm-arm64.h | 46 bool IsScratchRegister(const CPURegister& reg) {
80 void Load(const CPURegister& rd, const MemOperand& operand);
81 void Store(const CPURegister& rd, const MemOperand& operand);
141 CPURegister pending_register_;
|
| delayed-masm-arm64.cc | 98 void DelayedMasm::Load(const CPURegister& rd, const MemOperand& operand) {
133 void DelayedMasm::Store(const CPURegister& rd, const MemOperand& operand) {
|
| /art/compiler/optimizing/ |
| common_arm64.h | 124 inline vixl::aarch64::CPURegister CPURegisterFrom(Location location, DataType::Type type) {
126 ? vixl::aarch64::CPURegister(FPRegisterFrom(location, type))
127 : vixl::aarch64::CPURegister(RegisterFrom(location, type));
130 inline vixl::aarch64::CPURegister OutputCPURegister(HInstruction* instr) {
132 ? static_cast<vixl::aarch64::CPURegister>(OutputFPRegister(instr))
133 : static_cast<vixl::aarch64::CPURegister>(OutputRegister(instr));
136 inline vixl::aarch64::CPURegister InputCPURegisterAt(HInstruction* instr, int index) {
138 ? static_cast<vixl::aarch64::CPURegister>(InputFPRegisterAt(instr, index))
139 : static_cast<vixl::aarch64::CPURegister>(InputRegisterAt(instr, index));
142 inline vixl::aarch64::CPURegister InputCPURegisterOrZeroRegAt(HInstruction* instr
[all...] |
| code_generator_arm64.h | 93 vixl::aarch64::CPURegister::kRegister,
99 const vixl::aarch64::CPURegList callee_saved_fp_registers(vixl::aarch64::CPURegister::kFPRegister,
499 void MoveConstant(vixl::aarch64::CPURegister destination, HConstant* constant);
505 vixl::aarch64::CPURegister dst,
508 vixl::aarch64::CPURegister src,
511 vixl::aarch64::CPURegister dst,
516 vixl::aarch64::CPURegister src,
[all...] |
| /art/disassembler/ |
| disassembler_arm64.h | 48 const vixl::aarch64::CPURegister& reg) OVERRIDE;
|
| disassembler_arm64.cc | 45 const CPURegister& reg) {
|
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.cc | 447 CPURegister reg1,
448 CPURegister reg2,
449 CPURegister reg3,
450 CPURegister reg4) {
486 if (reg1.GetType() == CPURegister::kRRegister) {
489 if (reg2.GetType() == CPURegister::kRRegister) {
492 if (reg3.GetType() == CPURegister::kRRegister) {
495 if (reg4.GetType() == CPURegister::kRRegister) {
499 VIXL_ASSERT(tmp.GetType() == CPURegister::kRRegister);
610 void MacroAssembler::PushRegister(CPURegister reg)
[all...] |
| instructions-aarch32.h | 59 class CPURegister {
82 CPURegister(RegisterType type, uint32_t code, int size)
128 bool IsSameFormat(CPURegister reg) {
131 bool Is(CPURegister ref) const { return GetReg() == ref.GetReg(); }
135 class Register : public CPURegister {
137 Register() : CPURegister(kNoRegister, 0, kRegSizeInBits) {}
139 : CPURegister(kRRegister, code % kNumberOfRegisters, kRegSizeInBits) {
178 class VRegister : public CPURegister {
180 VRegister() : CPURegister(kNoRegister, 0, 0) {}
182 : CPURegister(type, code, size) {
[all...] |
