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  /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/
gen5_iosf_sb_definitions.h 29 #define DTR4 0x0005
meminit.c 389 // It will initialise timing registers in the MCU (DTR0..DTR4).
401 RegDTR4 Dtr4;
412 Dtr4.raw = isbR32m(MCU, DTR4);
471 Dtr4.field.WRODTSTRT = Dtr1.field.tCMD;
472 Dtr4.field.WRODTSTOP = Dtr1.field.tCMD;
473 Dtr4.field.RDODTSTRT = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2; //Convert from WL (DRAM clocks) to VLV indx
474 Dtr4.field.RDODTSTOP = Dtr1.field.tCMD + Dtr0.field.tCL - Dtr1.field.tWCL + 2;
475 Dtr4.field.TRGSTRDIS = 0;
476 Dtr4.field.ODTDIS = 0;
1385 RegDTR4 dtr4; local
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