| /toolchain/binutils/binutils-2.27/include/opcode/ |
| tic30.h | 198 #define Disp 0x0080
261 { "b" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
262 { "bu" ,1,0x68000000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
263 { "blo" ,1,0x68010000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
264 { "bls" ,1,0x68020000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
265 { "bhi" ,1,0x68030000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
266 { "bhs" ,1,0x68040000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
267 { "beq" ,1,0x68050000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
268 { "bne" ,1,0x68060000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None },
269 { "blt" ,1,0x68070000,PCRel, { AllReg|Disp, 0, 0 }, Imm_None }
[all...] |
| /external/swiftshader/third_party/subzero/src/ |
| IceInstX8664.cpp | 94 int32_t Disp = Var->getStackOffset();
97 Disp += Target->getFrameFixedAllocaOffset();
101 return Disp;
113 int32_t Disp = 0;
115 Disp += getRematerializableOffset(getBase(), Target);
125 if (getOffset() == nullptr && Disp == 0) {
127 } else if (getOffset() == nullptr && Disp != 0) {
128 Str << Disp;
130 if (Base == nullptr || CI->getValue() || Disp != 0)
132 Str << CI->getValue() + Disp;
[all...] |
| IceInstX8632.cpp | 104 int32_t Disp = Var->getStackOffset();
107 Disp += Target->getFrameFixedAllocaOffset();
111 return Disp;
140 int32_t Disp = 0;
142 Disp += getRematerializableOffset(getBase(), Target);
156 if (getOffset() == nullptr && Disp == 0) {
158 } else if (getOffset() == nullptr && Disp != 0) {
159 Str << Disp;
161 if (getBase() == nullptr || CI->getValue() || Disp != 0)
163 Str << CI->getValue() + Disp;
[all...] |
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 65 const MCOperand &Disp = MI->getOperand(OpNo+1);
78 if (Disp.isExpr())
79 Disp.getExpr()->print(O, &MAI);
81 assert(Disp.isImm() && "Expected immediate in displacement field");
82 O << Disp.getImm();
|
| /external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
| SystemZMCCodeEmitter.cpp | 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
153 assert(isUInt<4>(Base) && isUInt<12>(Disp));
154 return (Base << 12) | Disp;
162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
163 assert(isUInt<4>(Base) && isInt<20>(Disp));
164 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI);
174 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
175 return (Index << 16) | (Base << 12) | Disp;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 63 const MCOperand &Disp = MI->getOperand(OpNo+1);
76 if (Disp.isExpr())
77 O << *Disp.getExpr();
79 assert(Disp.isImm() && "Expected immediate in displacement field");
80 O << Disp.getImm();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 57 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 int64_t Disp;
64 : Form(form), DR(dr), Base(), Disp(0), Index(),
90 errs() << " Disp " << Disp;
158 SDValue &Base, SDValue &Disp) const;
160 SDValue &Base, SDValue &Disp, SDValue &Index) const;
164 // Base and Disp respectively.
166 SDValue &Base, SDValue &Disp) const;
170 // base and displacement in Base and Disp respectively
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
| SystemZISelDAGToDAG.cpp | 48 int64_t Disp;
52 : BaseType(RegBase), IndexReg(), Disp(0), isRI(RI) {
72 errs() << " Disp " << Disp << '\n';
86 SDValue &Base, SDValue &Disp);
88 SDValue &Base, SDValue &Disp,
124 SDValue &Base, SDValue &Disp);
126 SDValue &Base, SDValue &Disp,
128 bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp);
130 SDValue &Base, SDValue &Disp, SDValue &Index)
[all...] |
| SystemZInstrBuilder.h | 33 /// with R15 or R11 and Disp being offsetted accordingly.
46 int32_t Disp;
49 SystemZAddressMode() : BaseType(RegBase), IndexReg(0), Disp(0) {
98 return MIB.addImm(AM.Disp).addReg(AM.IndexReg);
|
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 47 int16_t Disp;
56 : BaseType(RegBase), Disp(0), GV(nullptr), CP(nullptr),
72 errs() << " Disp " << Disp << '\n';
118 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
144 AM.Disp += G->getOffset();
149 AM.Disp += CP->getOffset();
186 AM.Disp += Val;
229 AM.Disp += Offset;
244 SDValue &Base, SDValue &Disp) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 46 int16_t Disp;
55 : BaseType(RegBase), Disp(0), GV(0), CP(0), BlockAddr(0),
71 errs() << " Disp " << Disp << '\n';
123 bool SelectAddr(SDValue Addr, SDValue &Base, SDValue &Disp);
149 AM.Disp += G->getOffset();
154 AM.Disp += CP->getOffset();
191 AM.Disp += Val;
234 AM.Disp += Offset;
249 SDValue &Base, SDValue &Disp) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| X86InstrBuilder.h | 36 /// with BP or SP and Disp being offsetted accordingly. The displacement may
51 int Disp;
56 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
79 MO.push_back(MachineOperand::CreateImm(Disp));
136 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
138 MIB.addImm(AM.Disp);
|
| /external/v8/src/s390/ |
| assembler-s390.h | 334 typedef int32_t Disp;
343 explicit MemOperand(Register rx, Disp offset = 0);
344 explicit MemOperand(Register rx, Register rb, Disp offset = 0);
701 inline void name(R1 r1, Register x2, Register b2, Disp d2) { \
725 void bc(Condition cond, Register x2, Register b2, Disp d2) {
732 inline void name(R1 r1, R2 r2, Register b2, Disp d2) { \
758 void pfd(Condition cond, Register x2, Register b2, Disp d2) {
863 void name(Register r1, Register b2, Register x2, Disp d2)
867 void name(Register r1, Register r3, Register b2, Register x2, Disp d2)
[all...] |
| assembler-s390.cc | 683 void Assembler::name(Register r1, Register r3, Register b2, Disp d2) { \
691 const Disp d2) {
703 void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) { \
711 const Disp d2) {
739 void Assembler::name(Length l1, Register b2, Disp d2) { \
743 void Assembler::rsl_form(Opcode op, Length l1, Register b2, Disp d2) {
759 void Assembler::name(Register r1, Register r3, Register b2, Disp d2) { \
767 const Disp d2) {
786 void Assembler::name(Register r1, Condition m3, Register b2, Disp d2) { \
794 const Disp d2)
[all...] |
| /external/capstone/arch/SystemZ/ |
| SystemZDisassembler.c | 189 uint64_t Disp = Field & 0xfff;
193 MCOperand_CreateImm0(Inst, Disp);
202 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
206 MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
215 uint64_t Disp = Field & 0xfff;
219 MCOperand_CreateImm0(Inst, Disp);
230 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
234 MCOperand_CreateImm0(Inst, SignExtend64(Disp, 20));
245 uint64_t Disp = Field & 0xfff;
249 MCOperand_CreateImm0(Inst, Disp);
[all...] |
| SystemZInstPrinter.c | 42 static void printAddress(MCInst *MI, unsigned Base, int64_t Disp, unsigned Index, SStream *O)
44 if (Disp >= 0) {
45 if (Disp > HEX_THRESHOLD)
46 SStream_concat(O, "0x%"PRIx64, Disp);
48 SStream_concat(O, "%"PRIu64, Disp);
50 if (Disp < -HEX_THRESHOLD)
51 SStream_concat(O, "-0x%"PRIx64, -Disp);
53 SStream_concat(O, "-%"PRIu64, -Disp);
66 MI->flat_insn->detail->sysz.operands[MI->flat_insn->detail->sysz.op_count].mem.disp = Disp;
[all...] |
| /external/swiftshader/third_party/subzero/unittest/AssemblerX8664/ |
| GPRArith.cpp | 112 #define TestLeaBaseDisp(Base, BaseValue, Disp, Dst) \
121 Address(Encoded_GPR_##Base(), Disp, AssemblerFixup::NoFixup)); \
124 ASSERT_EQ(test.Base##d() + (Disp), test.Dst##d()) \
125 << TestString << " with Disp " << Disp; \
129 #define TestLeaIndex32bitDisp(Index, IndexValue, Disp, Dst0, Dst1, Dst2, Dst3) \
138 Address(Encoded_GPR_##Index(), Traits::TIMES_1, Disp, \
141 Address(Encoded_GPR_##Index(), Traits::TIMES_2, Disp, \
144 Address(Encoded_GPR_##Index(), Traits::TIMES_4, Disp, \
147 Address(Encoded_GPR_##Index(), Traits::TIMES_8, Disp, \
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86OptimizeLEAs.cpp | 71 const MachineOperand *Disp)
72 : Disp(Disp) {
89 return isSimilarDispOp(*Disp, *Other.Disp);
96 const MachineOperand *Disp;
119 assert(Val.Disp != PtrInfo::getEmptyKey() && "Cannot hash the empty key");
120 assert(Val.Disp != PtrInfo::getTombstoneKey() &&
130 switch (Val.Disp->getType()) {
135 Hash = hash_combine(Hash, Val.Disp->getIndex())
[all...] |
| X86InstrBuilder.h | 35 /// with BP or SP and Disp being offsetted accordingly. The displacement may
50 int Disp;
55 : BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(nullptr),
77 MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
79 MO.push_back(MachineOperand::CreateImm(Disp));
109 AM.Disp = Op.getImm();
164 MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
166 MIB.addImm(AM.Disp);
|
| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| MBlazeISelDAGToDAG.cpp | 86 bool SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base);
148 SelectAddrRegImm(SDValue N, SDValue &Base, SDValue &Disp) {
150 if (SelectAddrRegReg(N, Base, Disp))
156 Disp = CurDAG->getTargetConstant(imm, MVT::i32);
167 Disp = CurDAG->getTargetConstant(Imm, CN->getValueType(0));
172 Disp = CurDAG->getTargetConstant(0, TM.getTargetLowering()->getPointerTy());
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 134 const MCExpr *Disp;
173 return Mem.Disp;
339 static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
343 Res->Mem.Disp = Disp;
351 static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
363 Res->Mem.Disp = Disp;
378 isa<MCConstantExpr>(Op.Mem.Disp) &&
379 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &
[all...] |
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 310 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
312 getPointerWidth(), 0, Disp, SrcReg, 0, AccessSize, SMLoc(), SMLoc()));
319 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
321 getPointerWidth(), 0, Disp, SrcReg, CntReg, AccessSize, SMLoc(),
329 const MCExpr *Disp = MCConstantExpr::create(0, Ctx);
331 getPointerWidth(), 0, Disp, DstReg, 0, AccessSize, SMLoc(), SMLoc()));
337 const MCExpr *Disp = MCConstantExpr::create(-1, Ctx);
339 getPointerWidth(), 0, Disp, DstReg, CntReg, AccessSize, SMLoc(),
455 const MCConstantExpr *Disp =
458 X86Operand::CreateMem(getPointerWidth(), 0, Disp, Reg, 0, 1, SMLoc()
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 165 const MachineInstrBuilder &addDisp(const MachineOperand &Disp,
167 switch (Disp.getType()) {
171 return addImm(Disp.getImm() + off);
173 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off);
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 271 uint64_t Disp = Field & 0xfff;
274 Inst.addOperand(MCOperand::createImm(Disp));
281 uint64_t Disp = ((Field << 12) & 0xff000) | ((Field >> 8) & 0xfff);
284 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
292 uint64_t Disp = Field & 0xfff;
295 Inst.addOperand(MCOperand::createImm(Disp));
304 uint64_t Disp = ((Field & 0xfff00) >> 8) | ((Field & 0xff) << 12);
307 Inst.addOperand(MCOperand::createImm(SignExtend64<20>(Disp)));
316 uint64_t Disp = Field & 0xfff;
319 Inst.addOperand(MCOperand::createImm(Disp));
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 210 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
217 TargetFlags = Disp.getTargetFlags();
219 switch (Disp.getType()) {
223 return addImm(Disp.getImm() + off);
225 return addConstantPoolIndex(Disp.getIndex(), Disp.getOffset() + off,
228 return addGlobalAddress(Disp.getGlobal(), Disp.getOffset() + off,
|
