| /art/compiler/optimizing/ |
| intrinsics_mips64.cc | 436 __ Dsrl(TMP, in, 1);
442 __ Dsrl(TMP, TMP, 2);
445 __ Dsrl(out, TMP, 4);
855 __ Dsrl(TMP, TMP, 1); // TMP = 0 if AT = Long.MIN_VALUE
913 __ Dsrl(TMP, TMP, 1); // TMP = 0 if out = Long.MIN_VALUE
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| code_generator_mips64.cc | [all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 171 a->Dsrl(rd, rd, shift_cnt);
503 void Dsrl(GpuRegister rd, GpuRegister rt, int shamt); // MIPS64
[all...] |
| assembler_mips64_test.cc | [all...] |
| assembler_mips64.cc | 543 void Mips64Assembler::Dsrl(GpuRegister rd, GpuRegister rt, int shamt) {
[all...] |
