| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciPei/ |
| EhcPeim.c | 73 EhcWriteOpReg (
105 EhcWriteOpReg (Ehc, Offset, Data);
127 EhcWriteOpReg (Ehc, Offset, Data);
220 EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, Data);
237 EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
427 EhcWriteOpReg (Ehc, EHC_PORT_STAT_OFFSET + 4 * Index, RegVal);
486 EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, Ehc->High32bitAddr);
491 EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);
734 EhcWriteOpReg (Ehc, Offset, State);
746 EhcWriteOpReg (Ehc, Offset, State);
[all...] |
| EhciSched.c | 169 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, EHC_LOW_32BIT (Ehc->PeriodFrame));
176 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (Ehc->ReclaimHead));
191 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
192 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);
|
| EhciReg.h | 158 EhcWriteOpReg (
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/EhciDxe/ |
| EhciReg.c | 141 EhcWriteOpReg (
161 DEBUG ((EFI_D_ERROR, "EhcWriteOpReg: Pci Io Write error: %r at %d\n", Status, Offset));
185 EhcWriteOpReg (Ehc, Offset, Data);
208 EhcWriteOpReg (Ehc, Offset, Data);
327 EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, Data);
345 EhcWriteOpReg (Ehc, EHC_USBSTS_OFFSET, USBSTS_INTACK_MASK);
618 EhcWriteOpReg (Ehc, EHC_USBINTR_OFFSET, 0);
637 EhcWriteOpReg (Ehc, (UINT32) (EHC_PORT_STAT_OFFSET + (4 * Index)), RegVal);
|
| Ehci.c | 471 EhcWriteOpReg (Ehc, Offset, State);
476 EhcWriteOpReg (Ehc, Offset, State);
497 EhcWriteOpReg (Ehc, Offset, State);
506 EhcWriteOpReg (Ehc, Offset, State);
512 EhcWriteOpReg (Ehc, Offset, State);
578 EhcWriteOpReg (Ehc, Offset, State);
590 EhcWriteOpReg (Ehc, Offset, State);
598 EhcWriteOpReg (Ehc, Offset, State);
606 EhcWriteOpReg (Ehc, Offset, State);
614 EhcWriteOpReg (Ehc, Offset, State);
[all...] |
| EhciReg.h | 180 EhcWriteOpReg (
|
| EhciSched.c | 168 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, EHC_LOW_32BIT (PhyAddr));
172 EhcWriteOpReg (Ehc, EHC_CTRLDSSEG_OFFSET, EHC_HIGH_32BIT (PhyAddr));
224 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, EHC_LOW_32BIT (PciAddr));
264 EhcWriteOpReg (Ehc, EHC_FRAME_BASE_OFFSET, 0);
265 EhcWriteOpReg (Ehc, EHC_ASYNC_HEAD_OFFSET, 0);
|
