| /external/libjpeg-turbo/simd/ |
| jsimdcfg.inc.h | 107 %define FAST_FLOAT FP32 ; float
119 %define FLOAT_MULT_TYPE FP32 ; must be float
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegisterInfo.cpp | 48 for (auto Reg : {WebAssembly::SP32, WebAssembly::SP64, WebAssembly::FP32,
130 /* hasFP */ {WebAssembly::FP32, WebAssembly::FP64}};
|
| WebAssemblyFrameLowering.cpp | 172 WebAssembly::FP32)
208 .addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32)
211 SPReg = hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32;
|
| /external/eigen/Eigen/src/Core/arch/CUDA/ |
| Half.h | 32 // in fp32 for CPUs, except for simple parameter conversions, I/O
146 // these are no faster than fp32 arithmetic (you need to use the half2
205 // to/from fp32.
278 union FP32 {
293 FP32 f; f.f = ff;
295 const FP32 f32infty = { 255 << 23 };
296 const FP32 f16max = { (127 + 16) << 23 };
297 const FP32 denorm_magic = { ((127 - 15) + (23 - 10) + 1) << 23 };
346 const FP32 magic = { 113 << 23 };
348 FP32 o
[all...] |
| /external/swiftshader/third_party/subzero/pydir/ |
| gen_arm32_reg_tables.py | 109 FP32 = [
199 RegClasses = [('GPR', GPRs), ('I64PAIR', I64Pairs), ('FP32', FP32),
|
| /external/llvm/test/MC/SystemZ/ |
| regs-bad.s | 94 # Test FP32 operands
|
| /external/vixl/src/aarch64/ |
| constants-aarch64.h | 411 FP32 = 0x00000000,
430 NEON_FP_2S = FP32,
431 NEON_FP_4S = FP32 | NEON_Q,
[all...] |
| assembler-aarch64.h | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64-inl.h | 1184 return fd.Is64Bits() ? FP64 : FP32;
[all...] |
| constants-arm64.h | 412 FP32 = 0x00000000,
[all...] |
