| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/arm/ |
| vfp1xD.s | 86 fmrx r0, fpscr
93 fmxr fpscr, r0
353 vmrs r0, FPSCR
354 vmrs r1, FPSCR
355 vmrs r2, FPSCR
356 vmrs r3, FPSCR
357 vmrs r4, FPSCR
358 vmrs r5, FPSCR
359 vmrs r6, FPSCR
360 vmrs r7, FPSCR
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/internal/obj/ppc64/ |
| anames9.go | 36 "FPSCR",
|
| list9.go | 87 return "FPSCR"
|
| /prebuilts/go/linux-x86/src/cmd/internal/obj/ppc64/ |
| anames9.go | 36 "FPSCR",
|
| list9.go | 87 return "FPSCR"
|
| /external/valgrind/none/tests/arm/ |
| vfp.stdout.exp | [all...] |
| /external/valgrind/none/tests/ppc32/ |
| test_dfp1.stdout.exp | [all...] |
| /external/valgrind/none/tests/ppc64/ |
| test_dfp1.stdout.exp | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/asm/internal/asm/testdata/ |
| ppc64.s | 147 // LMOVW fpscr ',' freg
151 MOVFL FPSCR, F1
153 // LMOVW freg ',' fpscr
157 MOVFL F1, FPSCR
159 // LMOVW freg ',' imm ',' fpscr
163 MOVFL F1, $4, FPSCR
165 // LMOVW fpscr ',' creg
169 MOVFL FPSCR, CR0
331 // LMOVW psr ',' creg // TODO: should psr should be fpscr
335 //TODO 9a trouble MOVW FPSCR, CR
[all...] |
| /prebuilts/go/linux-x86/src/cmd/asm/internal/asm/testdata/ |
| ppc64.s | 147 // LMOVW fpscr ',' freg
151 MOVFL FPSCR, F1
153 // LMOVW freg ',' fpscr
157 MOVFL F1, FPSCR
159 // LMOVW freg ',' imm ',' fpscr
163 MOVFL F1, $4, FPSCR
165 // LMOVW fpscr ',' creg
169 MOVFL FPSCR, CR0
331 // LMOVW psr ',' creg // TODO: should psr should be fpscr
335 //TODO 9a trouble MOVW FPSCR, CR
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| inst.go | 225 FPSCR
240 case FPSCR:
241 return "FPSCR"
|
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| inst.go | 225 FPSCR
240 case FPSCR:
241 return "FPSCR"
|
| /toolchain/binutils/binutils-2.27/gas/testsuite/gas/sh/arch/ |
| sh2a-or-sh3e.s | 62 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
67 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
150 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
155 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh2e.s | 15 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
17 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
19 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
21 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh3e.s | 68 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
73 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
164 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
169 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh2a-or-sh4.s | 88 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
93 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
176 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
181 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh4.s | 77 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
82 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
181 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
186 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
[all...] |
| sh4a.s | 74 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
79 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
183 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
188 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
[all...] |
| /toolchain/binutils/binutils-2.27/ld/testsuite/ld-sh/arch/ |
| sh2a-or-sh3e.s | 62 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
67 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
150 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
155 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh2e.s | 15 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
17 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
19 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
21 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh3e.s | 68 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
73 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
164 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
169 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh2a-or-sh4.s | 88 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
93 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
176 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
181 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
|
| sh4.s | 77 lds r5,FPSCR ;!/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}
82 lds.l @r5+,FPSCR ;!/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}
181 sts FPSCR,r4 ;!/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}
186 sts.l FPSCR,@-r4 ;!/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}
[all...] |
| /external/vixl/src/aarch32/ |
| instructions-aarch32.cc | 365 case FPSCR:
366 return "FPSCR";
|
| /external/vixl/tools/test_generator/ |
| data_types.py | 521 class FPSCR(U32):
528 __ Vmsr(FPSCR, fpsr_bits);
537 __ Vmrs(RegisterOrAPSR_nzcv(fpsr_bits.GetCode()), FPSCR);
|
