| /external/llvm/lib/Target/Lanai/ |
| LanaiInstrInfo.cpp | 509 MachineOperand FalseReg = MI.getOperand(Invert ? 1 : 2);
511 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
534 // allocator ensure the FalseReg is allocated the same register as operand 0.
535 FalseReg.setImplicit();
536 NewMI.addOperand(FalseReg);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.h | 159 unsigned FalseReg) const override;
|
| AArch64InstrInfo.cpp | 368 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
373 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
389 else if (canFoldIntoCSel(MRI, FalseReg))
411 unsigned TrueReg, unsigned FalseReg) const {
517 // FalseReg, so we need to invert the condition.
519 TrueReg = FalseReg;
521 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
525 FalseReg = NewVReg;
534 MRI.constrainRegClass(FalseReg, RC);
537 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 182 unsigned FalseReg) const override;
|
| PPCInstrInfo.cpp | 687 unsigned TrueReg, unsigned FalseReg,
703 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
729 unsigned FalseReg) const {
739 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
740 assert(RC && "TrueReg and FalseReg must have overlapping register classes");
791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg,
792 SecondReg = SwapOps ? TrueReg : FalseReg;
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 672 /// instruction that chooses between TrueReg and FalseReg based on the
676 /// FalseReg, and Cond to the destination register. In most cases, a select
684 /// @param FalseReg Virtual register to select when Cond is false.
687 /// @param FalseCycles Latency from FalseReg to select output.
690 unsigned TrueReg, unsigned FalseReg,
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 678 /// instruction that chooses between TrueReg and FalseReg based on the
682 /// FalseReg, and Cond to the destination register. In most cases, a select
690 /// @param FalseReg Virtual register to select when Cond is false.
693 /// @param FalseCycles Latency from FalseReg to select output.
696 unsigned TrueReg, unsigned FalseReg
[all...] |
| /prebuilts/clang/host/darwin-x86/clang-4393122/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4479392/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4579689/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4630689/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4639204/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/darwin-x86/clang-4691093/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4053586/prebuilt_include/llvm/include/llvm/Target/ |
| TargetInstrInfo.h | 678 /// instruction that chooses between TrueReg and FalseReg based on the
682 /// FalseReg, and Cond to the destination register. In most cases, a select
690 /// @param FalseReg Virtual register to select when Cond is false.
693 /// @param FalseCycles Latency from FalseReg to select output.
696 unsigned TrueReg, unsigned FalseReg
[all...] |
| /prebuilts/clang/host/linux-x86/clang-4393122/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4479392/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4579689/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4630689/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4639204/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /prebuilts/clang/host/linux-x86/clang-4691093/include/llvm/Target/ |
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFastISel.cpp | 728 unsigned FalseReg = getRegForValue(Select->getFalseValue());
729 if (FalseReg == 0)
733 std::swap(TrueReg, FalseReg);
764 .addReg(FalseReg)
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86InstrInfo.h | 328 unsigned FalseReg) const override;
|
| X86InstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | [all...] |
