| /hardware/intel/img/psb_video/src/hwdefs/ |
| msvdx_vec_vp8_reg_io2.h | 55 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PARTITION_SIZE_N_VP8_FE_PARTITION_SIZE_SIGNED_FIELD IMG_FALSE
63 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_FRAME_TYPE_SIGNED_FIELD IMG_FALSE
69 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_NUM_PARTITION_MINUS1_SIGNED_FIELD IMG_FALSE
75 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_SEG_ID_CTRL_SIGNED_FIELD IMG_FALSE
81 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC0_VP8_FE_UPDATE_SEGMENTATION_MAP_SIGNED_FIELD IMG_FALSE
89 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_HEIGHT_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE
95 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC1_VP8_FE_PIC_WIDTH_IN_MBS_LESS1_SIGNED_FIELD IMG_FALSE
103 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_DECODE_PRED_NOT_COEFFS_SIGNED_FIELD IMG_FALSE
109 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_MB_NO_COEFF_SKIP_SIGNED_FIELD IMG_FALSE
115 #define MSVDX_VEC_VP8_CR_VEC_VP8_FE_PIC2_VP8_FE_SIGN_BIAS_FOR_GF_SIGNED_FIELD IMG_FALSE
[all...] |
| msvdx_vec_jpeg_reg_io2.h | 53 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_COMPONENTS_FE_COMPONENTS_SIGNED_FIELD IMG_FALSE
59 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_COMPONENTS_MAX_H_SIGNED_FIELD IMG_FALSE
65 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_COMPONENTS_MAX_V_SIGNED_FIELD IMG_FALSE
71 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_COMPONENTS_RESTART_SIGNED_FIELD IMG_FALSE
79 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_HEIGHT_FE_HEIGHT_MINUS1_SIGNED_FIELD IMG_FALSE
87 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_RESTART_POS_MCU_ROW_POSITION_SIGNED_FIELD IMG_FALSE
93 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_RESTART_POS_MCU_COLUMN_POSITION_SIGNED_FIELD IMG_FALSE
99 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_RESTART_POS_USE_SOFTWARE_POSITION_SIGNED_FIELD IMG_FALSE
107 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_WIDTH_FE_WIDTH_MINUS1_SIGNED_FIELD IMG_FALSE
115 #define MSVDX_VEC_JPEG_CR_VEC_JPEG_FE_ENTROPY_CODING_NUM_MCUS_LESS1_SIGNED_FIELD IMG_FALSE
[all...] |
| msvdx_vec_vp8_line_store_mem_io2.h | 53 #define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_00_SIGNED_FIELD IMG_FALSE
59 #define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_01_SIGNED_FIELD IMG_FALSE
65 #define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SEGMENT_ID_PROBS_02_SIGNED_FIELD IMG_FALSE
71 #define MSVDX_VEC_LINE_STORE_RAM_MB_START_PROBS_REG_00_SKIP_FALSE_PROBS_00_SIGNED_FIELD IMG_FALSE
79 #define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_00_SIGNED_FIELD IMG_FALSE
85 #define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_01_SIGNED_FIELD IMG_FALSE
91 #define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_02_SIGNED_FIELD IMG_FALSE
97 #define MSVDX_VEC_LINE_STORE_RAM_Y_MODE_PROBS_REG_00_Y_MODE_PROBS_03_SIGNED_FIELD IMG_FALSE
105 #define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_00_SIGNED_FIELD IMG_FALSE
111 #define MSVDX_VEC_LINE_STORE_RAM_UV_MODE_PROBS_REG_00_UV_MODE_PROBS_01_SIGNED_FIELD IMG_FALSE
[all...] |
| msvdx_cmds_io2.h | 61 #define MSVDX_CMDS_HORIZONTAL_LUMA_COEFFICIENTS_HOR_LUMA_COEFF_3_SIGNED_FIELD IMG_FALSE
67 #define MSVDX_CMDS_HORIZONTAL_LUMA_COEFFICIENTS_HOR_LUMA_COEFF_2_SIGNED_FIELD IMG_FALSE
73 #define MSVDX_CMDS_HORIZONTAL_LUMA_COEFFICIENTS_HOR_LUMA_COEFF_1_SIGNED_FIELD IMG_FALSE
79 #define MSVDX_CMDS_HORIZONTAL_LUMA_COEFFICIENTS_HOR_LUMA_COEFF_0_SIGNED_FIELD IMG_FALSE
89 #define MSVDX_CMDS_VERTICAL_LUMA_COEFFICIENTS_VER_LUMA_COEFF_3_SIGNED_FIELD IMG_FALSE
95 #define MSVDX_CMDS_VERTICAL_LUMA_COEFFICIENTS_VER_LUMA_COEFF_2_SIGNED_FIELD IMG_FALSE
101 #define MSVDX_CMDS_VERTICAL_LUMA_COEFFICIENTS_VER_LUMA_COEFF_1_SIGNED_FIELD IMG_FALSE
107 #define MSVDX_CMDS_VERTICAL_LUMA_COEFFICIENTS_VER_LUMA_COEFF_0_SIGNED_FIELD IMG_FALSE
117 #define MSVDX_CMDS_HORIZONTAL_CHROMA_COEFFICIENTS_HOR_CHROMA_COEFF_3_SIGNED_FIELD IMG_FALSE
123 #define MSVDX_CMDS_HORIZONTAL_CHROMA_COEFFICIENTS_HOR_CHROMA_COEFF_2_SIGNED_FIELD IMG_FALSE
[all...] |
| img_types.h | 87 IMG_FALSE = 0,
|
| topazhp_default_params.h | 73 #define TOPAZHP_DEFAULT_bPowerTest IMG_FALSE
|
| msvdx_vec_reg_io2.h | 142 #define MSVDX_VEC_CR_VEC_ENTDEC_BE_CONTROL_ENTDEC_BE_EXTENDED_MODE_SIGNED_FIELD IMG_FALSE
[all...] |
| /hardware/intel/img/psb_video/src/ |
| tng_MPEG4ES.c | 154 ctx->bIsInterlaced = IMG_FALSE;
155 ctx->bIsInterleaved = IMG_FALSE;
173 ctx->bEnableHostQP = IMG_FALSE;
182 ctx->bEnableInpCtrl = IMG_FALSE;
183 ctx->bEnableHostBias = IMG_FALSE;
185 ctx->bEnableCumulativeBiases = IMG_FALSE;
188 ctx->bWeightedPrediction = IMG_FALSE;
193 ctx->bArbitrarySO = IMG_FALSE;
250 ctx->bCustomScaling = IMG_FALSE;
251 ctx->bUseDefaultScalingList = IMG_FALSE;
[all...] |
| tng_H263ES.c | 154 ctx->bIsInterlaced = IMG_FALSE;
155 ctx->bIsInterleaved = IMG_FALSE;
161 ctx->bEnableHostQP = IMG_FALSE;
170 ctx->bEnableInpCtrl = IMG_FALSE;
171 ctx->bEnableHostBias = IMG_FALSE;
173 ctx->bEnableCumulativeBiases = IMG_FALSE;
176 ctx->bWeightedPrediction = IMG_FALSE;
181 ctx->bArbitrarySO = IMG_FALSE;
241 ctx->bCustomScaling = IMG_FALSE;
242 ctx->bUseDefaultScalingList = IMG_FALSE;
[all...] |
| tng_hostcode.c | 375 pEncFeatures->bDisableBPicRef_0 = IMG_FALSE;
376 pEncFeatures->bDisableBPicRef_1 = IMG_FALSE;
378 pEncFeatures->bDisableInter8x8 = IMG_FALSE;
379 pEncFeatures->bRestrictInter4x4 = IMG_FALSE;
381 pEncFeatures->bDisableIntra4x4 = IMG_FALSE;
382 pEncFeatures->bDisableIntra8x8 = IMG_FALSE;
383 pEncFeatures->bDisableIntra16x16 = IMG_FALSE;
387 pEncFeatures->bDisableBFrames = IMG_FALSE;
403 pEncFeatures->bDisableBPicRef_0 = IMG_FALSE;
404 pEncFeatures->bDisableBPicRef_1 = IMG_FALSE;
[all...] |
| tng_H264ES.c | 153 ctx->bIsInterlaced = IMG_FALSE;
154 ctx->bIsInterleaved = IMG_FALSE;
167 ctx->bEnableHostQP = IMG_FALSE;
176 ctx->bEnableInpCtrl = IMG_FALSE;
177 ctx->bEnableHostBias = IMG_FALSE;
179 ctx->bEnableCumulativeBiases = IMG_FALSE;
182 ctx->bWeightedPrediction = IMG_FALSE;
184 ctx->bInsertHRDParams = IMG_FALSE;
185 ctx->bArbitrarySO = IMG_FALSE;
188 ctx->bVPAdaptiveRoundingDisable = IMG_FALSE;
[all...] |
| pnw_H264ES.c | 136 ctx->sRCParams.bDisableBitStuffing = IMG_FALSE;
143 ctx->sRCParams.RCEnable = IMG_FALSE;
144 ctx->sRCParams.bDisableBitStuffing = IMG_FALSE;
148 ctx->sRCParams.bDisableBitStuffing = IMG_FALSE;
241 IMG_FALSE : IMG_TRUE);
338 ctx->bInsertVUI = pSequenceParams->vui_parameters_present_flag ? IMG_TRUE: IMG_FALSE;
679 pnw__H264_prepare_picture_header(cmdbuf->header_mem_p + ctx->pic_header_ofs, IMG_FALSE, ctx->sRCParams.QCPOffset);
764 IMG_FALSE,
765 IMG_FALSE,
[all...] |
| tng_hostheader.c | 380 static IMG_BOOL bStartNextRawDataElement = IMG_FALSE;
386 bStartNextRawDataElement = IMG_FALSE;
[all...] |
| tng_hostbias.c | 44 #define TOPAZHP_DEFAULT_bZeroDetectionDisable IMG_FALSE
232 uiDCScaleL = CalculateDCScaler(n, IMG_FALSE);
298 uiDCScaleL = CalculateDCScaler(n, IMG_FALSE);
|
| pnw_MPEG4ES.c | 139 ctx->sRCParams.RCEnable = IMG_FALSE;
344 bIsVOPCoded = IMG_FALSE;*/
365 IMG_FALSE,
|
| tng_picmgmt.c | 104 IMG_FALSE;
109 IMG_FALSE;
110 bUsesLongTermRef1 = IMG_FALSE;
209 if (ctx->bCustomScaling == IMG_FALSE) {
[all...] |
| pnw_hostcode.c | 211 uiDCScaleL = CalculateDCScaler(n, IMG_FALSE);
268 uiDCScaleL = CalculateDCScaler(n, IMG_FALSE);
553 ctx->SliceHeaderReady[i] = IMG_FALSE;
582 ctx->sRCParams.FrameSkip = IMG_FALSE;
633 ctx->sRCParams.bBitrateChanged = IMG_FALSE;
639 ctx->SliceHeaderReady[i] = IMG_FALSE;
802 psPicParams->IsPerSliceOutput = IMG_FALSE;
[all...] |
| pnw_H263ES.c | 137 ctx->sRCParams.RCEnable = IMG_FALSE;
|
| tng_hostair.c | 290 IMG_BOOL bRefresh=IMG_FALSE;
357 bRefresh = IMG_FALSE;
412 //IMG_BOOL bRefresh = IMG_FALSE;
[all...] |
| psb_cmdbuf.c | [all...] |
| /hardware/intel/img/psb_video/src/mrst/ |
| lnc_MPEG4ES.c | 150 ctx->sRCParams.RCEnable = IMG_FALSE;
306 bIsVOPCoded = IMG_FALSE;
395 IMG_FALSE, /* Deblock is off for MPEG4*/
|
| lnc_H264ES.c | 156 ctx->sRCParams.RCEnable = IMG_FALSE;
266 sCrop.bClip = IMG_FALSE;
493 deblock_on = IMG_FALSE;
[all...] |
| psb_MPEG2MC.c | [all...] |
| lnc_H263ES.c | 146 ctx->sRCParams.RCEnable = IMG_FALSE;
|
| lnc_hostcode.c | 512 deblock_on = IMG_FALSE;
544 IMG_FALSE /* bIsVOPCoded is false now */,
[all...] |
